SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
In the same way that PRGs control and provide output from the POKs, the VTM controls and outputs signals from several temperature sensors that are spread around the die. The VTM provides three interrupts / ESM inputs to the system as well as a warm reset.
When the temperature sensor is enabled, it senses the temperature and reports the temperature as a 10-bit value.
Each of these comparisons can be individually enabled (VTM_CFG1_TMPSENS_CTRL_J and VTM_CFG1_TMPSENS_CTRL_J within mmr_vbusp_cfg2). Additionally, each temperature sensor has status bits for these comparator outputs in VTM_CFG1_TMPSENS_STAT_J.
The comparator functionality that drives the interrupts and warm reset work only when the sensor is configured for continuous mode; continuous operation becomes a de facto requirement (and is set in VTM_CFG1_TMPSENS_CTRL_J [4].CONT within mmr_vbusp_cfg2 – that is, the mode is set for each temperature sensor).
Interrupts / ESM inputs:
The comparator thresholds shall always configured so that TH2 > TH1 > TH0. The concept is:
LT_TH0_INT, if enabled, will get triggered always when the temperature being read is less than TH0, regardless of whether TH1 interrupt and TH2 interrupt are enabled or have ever been triggered. Therefore if TH0 interrupt is generated, then firmware/software is responsible to enable the TH0 interrupt only as part of the interrupt service routine of TH1 and TH2. Otherwise it will keep triggering when is not needed.
Warm Reset input:
Similar to the interrupts / ESM inputs, the warm reset generation is triggered off a threshold defined in VTM_CFG2_MISC_CTRL2[9-0] MAXT_OUTRG_ALERT_THR. The reset will be released when the compared temperature drops below VTM_CFG2_MISC_CTRL2[25-16] MAXT_OUTRG_ALERT_THR0.
VTM muxing of the temperature comparisons:
The VTM is configured by voltage domains. At this level, all the interrupt / ESM inputs from each temperature sensor can be enabled or disabled; as an example, the comparator outputs from temperature sensor 0 can be ignored in voltage domain 0. The enable is configured with the VTM_CFG1_VD_EVT_SET_J and VTM_CFG1_VD_EVT_CLR_J registers. At the voltage domain-level, the enabled comparator results are combined by interrupt / ESM signal. The combined comparator result can be observed in VTM_CFG1_VD_EVT_STAT_J. As is shown in the following table, j increments over voltage domains for these registers (see VTM Voltage Domains). The registers TMPSENS_*_j map to the individual temp sensors.
| Register Group | Voltage Domain |
|---|---|
| WKUP_VTM_*_VD_*_0 | VDD_MCU |
| WKUP_VTM_*_VD_*_1 | VDD_CORE |
| others | Unused |
After the temperature sensors are combined at a voltage domain level, the outputs from each voltage domain are enabled at the top level of the VTM with VTM_CFG1_GT_TH2_INT_EN_SET / VTM_CFG1_GT_TH2_INT_EN_CLR, VTM_CFG1_GT_TH1_INT_EN_SET / VTM_CFG1_GT_TH1_INT_EN_CLR, and VTM_CFG1_LT_TH0_INT_EN_SET / VTM_CFG1_LT_TH0_INT_EN_CLR. At this top level of the VTM, the status of these signals is checked and cleared with VTM_CFG1_GT_TH2_INT_RAW_STAT_SET / VTM_CFG1_GT_TH2_INT_EN_STAT_CLR, VTM_CFG1_GT_TH1_INT_RAW_STAT_SET / VTM_CFG1_GT_TH1_INT_EN_STAT_CLR, and VTM_CFG1_LT_TH0_INT_RAW_STAT_SET / VTM_CFG1_LT_TH0_INT_EN_STAT_CLR.