SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Selects the clock source for the AUDIO_EXT_REFCLK0 output, and direction.
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 A2E8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| AUDIO_REFCLK2_CTRL_CLKOUT_EN_PROXY | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | AUDIO_REFCLK2_CTRL_CLK_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | Fh | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15 | AUDIO_REFCLK2_CTRL_CLKOUT_EN_PROXY | R/W | 0h | AUDIO_REFCLK 2 output enable Field values (others are reserved): 1'b0 - INPUT 1'b1 - OUTPUT Reset Source: mod_g_rst_n |
| 14:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | AUDIO_REFCLK2_CTRL_CLK_SEL_PROXY | R/W | Fh | Selects the source of AUDIO_REFCLK2 Field values (others are reserved): 4'b0000 - MCASP0_AHCLKR 4'b0001 - MCASP1_AHCLKR 4'b0010 - MCASP2_AHCLKR 4'b0011 - MCASP3_AHCLKR 4'b0100 - MCASP4_AHCLKR 4'b0101 - MCASP0_AHCLKX 4'b0110 - MCASP1_AHCLKX 4'b0111 - MCASP2_AHCLKX 4'b1000 - MCASP3_AHCLKX 4'b1001 - MCASP4_AHCLKX 4'b1010 - ATCLK0 4'b1011 - ATCLK1 4'b1100 - ATCLK2 4'b1101 - ATCLK3 4'b1110 - MAIN_PLL1_HSDIV6_CLKOUT undefined - undefined 4'b1111 - MAIN_PLL4_HSDIV0_CLKOUT Reset Source: mod_g_rst_n |