SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Table 12-78 shows the software procedure to put MLBSS into standby mode.
| Step | Register/ Bit Field/ Programming Model/ Comments | Value |
|---|---|---|
| Ensure that there are no more transfers pending on both ends - system memory and MediaLB | No more data has to be transmitted from system memory to MediaLB and no more data has to be transmitted from MediaLB to system memory | - |
| Check if on system memory side all DMA transfers (receiving from MediaLB and transmitting to MediaLB) are completed | Read the DNE1 and DNE2 bits in the associated DDT channel descriptor of all enabled channels(1) | 1h |
| Ensure that no more valid data is received or transmitted on MediaLB. | This means that all expected packets/messages have been transferred out of the MLBSS internal data buffer. For asynchronous and isochronous control this can be confirmed by reading the write (WSTS) and read status (RSTS) of the CDT which indicates if a channel is active or idle. For synchronous control this check is not possible, since MediaLB channels always have some data to transmit or receive on an enabled MediaLB channel, no matter if this data is valid from a system software standpoint. | - |
| Disable MediaLB | MLB_MLBC0[0] MLBEN | 0h |
| Disable HBI | MLB_HCTL[15] EN | 0h |
| Disable DDT and CDT channels | Clear the associated channel enable bits in the CAT, DDT and CDT | 0h |
| Stop the MLBSS clocks | At this point no data transfers can occur in the MLBSS and the clocks MLBSS_SCLK, MLBSS_HCLK and MLBSS_PCLK can be stopped | - |