SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Interrupt Enable Set Register 0
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0070 4180h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | RAMECC19_ENABLE_SET | RAMECC18_ENABLE_SET | RAMECC17_ENABLE_SET | RAMECC16_ENABLE_SET | |||
| NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RAMECC15_ENABLE_SET | RAMECC14_ENABLE_SET | RAMECC13_ENABLE_SET | RAMECC12_ENABLE_SET | RAMECC11_ENABLE_SET | RAMECC10_ENABLE_SET | RAMECC9_ENABLE_SET | RAMECC8_ENABLE_SET |
| R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RAMECC7_ENABLE_SET | RAMECC6_ENABLE_SET | RAMECC5_ENABLE_SET | RAMECC4_ENABLE_SET | RAMECC3_ENABLE_SET | RAMECC2_ENABLE_SET | RAMECC1_ENABLE_SET | RAMECC0_ENABLE_SET |
| R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:20 | RESERVED | NONE | 0h | Reserved |
| 19 | RAMECC19_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc19_pend |
| 18 | RAMECC18_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc18_pend |
| 17 | RAMECC17_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc17_pend |
| 16 | RAMECC16_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc16_pend |
| 15 | RAMECC15_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc15_pend |
| 14 | RAMECC14_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc14_pend |
| 13 | RAMECC13_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc13_pend |
| 12 | RAMECC12_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc12_pend |
| 11 | RAMECC11_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc11_pend |
| 10 | RAMECC10_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc10_pend |
| 9 | RAMECC9_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc9_pend |
| 8 | RAMECC8_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc8_pend |
| 7 | RAMECC7_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc7_pend |
| 6 | RAMECC6_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc6_pend |
| 5 | RAMECC5_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc5_pend |
| 4 | RAMECC4_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc4_pend |
| 3 | RAMECC3_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc3_pend |
| 2 | RAMECC2_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc2_pend |
| 1 | RAMECC1_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc1_pend |
| 0 | RAMECC0_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for ramecc0_pend |