SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This is the POR reset signal (active LOW) for the entire device, controlled by the MCU_PORz HW Pin.
When LOW, it performs a POR reset on the entire device (Top Level and MAIN domains) and puts IOs in a safe state (as defined in the BALL STATE DURING RESET column of the datasheet Pin Attributes table).
All modules in the domain are reset.
Top Level IOs (IOs beginning with MCU_) are in HHV state (Reset State).
When MCU_PORz is de-asserted, the Os will enter the default state defined in the device Datasheet. The domain will be reconfigured by the device boot processor (secondary boot loader).
All modules in the MAIN domain are reset.
MAIN domain IOs are in HHV state (as defined in the BALL STATE DURING RESET column of the datasheet Pin Attributes table).
When MCU_PORz is de-asserted, the MAIN domain IOs will enter default state as defined in the BALL STATE AFTER RESET column of the datasheet Pin Attributes table.
The device boot processor (secondary boot loader) will setup R5FSS as Safety or General-Purpose Processor.