SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Timer Synchronous Interface Control Register
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| TIMER0 | 0240 0054h |
| TIMER1 | 0241 0054h |
| TIMER2 | 0242 0054h |
| TIMER3 | 0243 0054h |
| TIMER4 | 0244 0054h |
| TIMER5 | 0245 0054h |
| TIMER6 | 0246 0054h |
| TIMER7 | 0247 0054h |
| TIMER8 | 0248 0054h |
| TIMER9 | 0249 0054h |
| TIMER10 | 024A 0054h |
| TIMER11 | 024B 0054h |
| TIMER12 | 024C 0054h |
| TIMER13 | 024D 0054h |
| TIMER14 | 024E 0054h |
| TIMER15 | 024F 0054h |
| WKUP_TIMER0 | 2B10 0054h |
| WKUP_TIMER1 | 2B11 0054h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | READ_AFTER_IDLE | READ_MODE | POSTED | SFT | RESERVED | ||
| NONE | W | W | R/W | R/W | NONE | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:5 | RESERVED | NONE | 0h | Reserved |
| 4 | READ_AFTER_IDLE | W | 0h | Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active 0 The synchronization mechanism is enabled 1 The synchronization mechanism is disabled |
| 3 | READ_MODE | W | 0h | Select posted/non-posted mode for read operation.
This bit is not used when configured in posted mode 0 When the module is configurated in non-
posted mode the read operation is executed
as posted read
1 When the module is configured in non-posted
mode the read operation is executed as read
non-posted |
| 2 | POSTED | R/W | 0h | Reset value of POSTED depends on hardware integration module at design time.
Software must read POSTED field to get the hardwar module configuration 0 Posted mode inactive: will delay the
command accept output signal
1 Posted mode active |
| 1 | SFT | R/W | 0h | This bit reset all the functional part of teh module 0 Software reset is disabled 1 Software reset is enabled |
| 0 | RESERVED | NONE | 0h | Reserved |