SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Configures the USB0 Phy operation
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4300 6008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| USB0_PHY_CTRL_CORE_VOLTAGE_PROXY | RESERVED | ||||||
| R/W | NONE | ||||||
| 1h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | USB0_PHY_CTRL_PLL_REF_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 6h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | USB0_PHY_CTRL_CORE_VOLTAGE_PROXY | R/W | 1h | Selects the USB PHY Core Voltage Option: 0.85V or 0.75/0.80V Field values (others are reserved): 1'b0 - V_0P85 1'b1 - V_0P75_0P80 Reset Source: mod_g_rst_n |
| 30:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | USB0_PHY_CTRL_PLL_REF_SEL_PROXY | R/W | 6h | Indicates the frequency of the REF_CLOCK input used by the USB PLL. This value should be set to match the frequency of the USB0 input clock, as selected by the USB0_CLKSEL register Field values (others are reserved): 4'b0000 - MHZ_9P6 4'b0001 - MHZ_10 4'b0010 - MHZ_12 4'b0011 - MHZ_19P2 4'b0100 - MHZ_20 4'b0101 - MHZ_24 4'b0110 - MHZ_25 4'b0111 - MHZ_26 4'b1000 - MHZ_38P4 4'b1001 - MHZ_40 4'b1010 - MHZ_48 4'b1011 - MHZ_50 4'b1100 - MHZ_52 Reset Source: mod_g_rst_n |