SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
MAIN_R5FSS and WKUP_R5F include an Arm Cortex R5 with embedded debug capability, including:
A summary of the MAIN_R5FSS and WKUP_R5F debug capabilities is detailed in the following table
| Capability | Feature | Notes |
|---|---|---|
| Basic Debug | Independent debug configuration |
Debug resource configuration is performed over a configuration interface that is isolated from functional traffic |
| ROM Table | Facilitates discovery of debug resources within debug configuration address space | |
| Processor Halt | Support user-requested entry into the suspended stat | |
| Single Step | Execution of a single instruction before entering the suspended state | |
| Software Breakpoints | Software breakpoints are supported via opcode replacement | |
| Hardware Breakpoints | Eight Debug Breakpoint resources support hardware breakpoints | |
| Hardware Watchpoints | Eight Debug Watchpoint resources support data address breakpoints | |
| Core Register Access | Access to processor core registers | |
| System Memory Access | Access to memory from perspective of CPU | |
| Vector Catch | Halting in response to an exception | |
| Arm TrustZone Debug Authentication | Provisioning for DBGEN and NIDEN | |
| Cross Triggering | Debug State |
Support for controlling execution state (run, halt) via triggers and creating triggers upon entry into debug state |
| PMU | PMU interrupt trigger | |
| ETM |
Five ETM external triggers (one ETM Trigger, two external out event triggers, two external in event triggers) |
|
| PMU | Profile Counters |
Three counters can be used to count different events available for gathering statistics on the operation of the processor and memory system |
| Cycle Counters | One dedicated counter available for counting CPU clock cycles | |
| ETM | Triggering Infrastructure |
Comprehensive triggering infrastructure supports use of comparators (address, data value, context ID), counters, sequencer state, an external inputs and outputs to control the enabling of trace |
| Instruction Trace | Supports tracing of instruction flow | |
| Cycle-Accurate Tracing | Supports inclusion of a precise cycle count of executed instructions | |
| Branch Broadcast Tracing |
Support for tracing branch address details even in circumstances where that information might be discoverable from object code |
|
| Data Tracing | Support for data address and data value tracing |