SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This is the value of the next timestamp for the input clock generator 2. This contains the first 16 bits of the integer. This register is used to generate soft clock.
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| Instance Name | Physical Address |
|---|---|
| AASRC0 | 02D0 0304h |
| AASRC1 | 02D4 0304h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| STAMP_INT_HI | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STAMP_INT_HI | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | R | 0h | Always read as 0 |
| 15:0 | STAMP_INT_HI | R/W | 0h | This is the upper 16 bits of the integer multiple of the next timestamp for the clock source This register will be updated by adding the Clock Generator Rate to the Stamp value whenever the Free Running Counter passes the Stamp value |