SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
See reference [R1].
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| Instance Name | Physical Address |
|---|---|
| MLB0 | 02F8 23C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSV1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSV1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSV1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSV1 | MPB | RSV0 | DMAMODE | SMX | SCE | ||
| R/W | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:5 | RSV1 | R/W | 0h | Reserved (write default value) Reset Source: prst_n |
| 4 | MPB | R/W | 0h | Packet buffering mode: 0 = single-packet mode 1 = multiple-packet mode Reset Source: prst_n |
| 3 | RSV0 | R/W | 0h | Reserved (write default value) Reset Source: prst_n |
| 2 | DMAMODE | R/W | 0h | DMA Mode: 0 = DMA Mode 0 1 = DMA Mode 1 Reset Source: prst_n |
| 1 | SMX | R/W | 0h | AHB interrupt mux enable: 0 = ACSR0 generates an interrupt on ahb_int[0]; ACSR1 generates an interrupt on ahb_int[1] 1 = ACSR0 and ACSR1 generate an interrupts on ahb_int[0] only Reset Source: prst_n |
| 0 | SCE | R/W | 0h | Software clear enable: 0 = Hardware clears interrupt after a ACSRn register read 1 = Software clears interrupt Reset Source: prst_n |