SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This is the value of the rate for the clock generator 1. This contains the 24 bit fractional and the first 8 bits of the integer. This is based on a free running counter running on sys_clk. This register is used to generate soft clock.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| AASRC0 | 02D0 0288h |
| AASRC1 | 02D4 0288h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RATE_INT_LO | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| FRACTIONAL_STAMP | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| FRACTIONAL_STAMP | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FRACTIONAL_STAMP | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | RATE_INT_LO | R/W | 0h | This is the lower 8 bits of the integer multiple of the rate for the clock source This register will be added with the Clock Generator Stamp to update the Stamp value whenever the Free Running Counter passes the Stamp value |
| 23:0 | FRACTIONAL_STAMP | R/W | 0h | This is the fractional portion of the rate for the clock source |