SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Controls operation of ADC0
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 44D0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | ADC0_CTRL_GPI_MODE_EN | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ADC0_CTRL_TRIG_SEL | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:17 | RESERVED | NONE | 0h | Reserved |
| 16 | ADC0_CTRL_GPI_MODE_EN | R/W | 0h | Enables ADC0 data pins to be used as general purpose inputs when set. This signal is tied to the en_dig_test input of MCU_ADC0 Reset Source: mod_g_rst_n |
| 15:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | ADC0_CTRL_TRIG_SEL | R/W | 0h | Selects the source of the ADC hardware event trigger Field values (others are reserved): 5'b00000 - ADC_EXT_TRIGGER0 (Pin) 5'b00001 - 0 - Reserved 5'b00010 - EPWM SOCA_OUT 5'b00011 - EPWM SOCB_OUT 5'b00100 - 0 - Reserved 5'b00101 - 0 - Reserved 5'b00110 - 0 - Reserved 5'b00111 - 0 - Reserved 5'b01000 - 0 - Reserved 5'b01001 - 0 - Reserved 5'b01010 - 0 - Reserved 5'b01011 - 0 - Reserved 5'b01100 - 0 - Reserved 5'b01101 - 0 - Reserved 5'b01110 - WKUP_TIMER0 PWM 5'b01111 - WKUP_TIMER1 PWM 5'b10000 - TIMER0 PWM 5'b10001 - TIMER1 PWM 5'b10010 - TIMER2 PWM 5'b10011 - TIMER3 PWM 5'b10100 - TIMER4 PWM 5'b10101 - TIMER5 PWM 5'b10110 - TIMER6 PWM 5'b10111 - TIMER7 PWM 5'b11000 - TIMER8 PWM 5'b11001 - TIMER9 PWM 5'b11010 - TIMER10 PWM 5'b11011 - TIMER11 PWM 5'b11100 - TIMER12 PWM 5'b11101 - TIMER13_PWM 5'b11110 - TIMER14_pWM 5'b11111 - Timer15_PWM Reset Source: mod_g_rst_n |