SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The priority control register is used to control the priority of the transactions which the DMA generates on it's initiator interface.
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| Instance Name | Physical Address |
|---|---|
| DMASS0_PKTDMA_0 | 484C 0064h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PRIORITY | RESERVED | |||||
| NONE | R/W | NONE | |||||
| 0h | 0h | 0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ORDERID | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | NONE | 0h | Reserved |
| 30:28 | PRIORITY | R/W | 0h | Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel. Reset Source: rst_mod_g_rst_n |
| 27:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | ORDERID | R/W | 0h | Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel. Reset Source: rst_mod_g_rst_n |