SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Configures cluster level characteristics
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| Instance Name | Physical Address |
|---|---|
| WKUP_WKUP_SEC_MMR0 | 45A3 C040h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLSTR28_CFG_SINGLE_CORE_ONLY | CLSTR28_CFG_SINGLE_CORE | CLSTR28_CFG_MEM_INIT_DIS | CLSTR28_CFG_LOCKSTEP_EN | CLSTR28_CFG_DBG_NO_CLKSTOP | CLSTR28_CFG_TEINIT | CLSTR28_CFG_LOCKSTEP | |
| R | R | R/W | R | R/W | R/W | R | |
| 0h | 1h | 1h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 6 | CLSTR28_CFG_SINGLE_CORE_ONLY | R | 1h | Single / Dual CPU Mode Supported: 0 = Both Dual and Single Core are supported 1 = Only Single Core Mode is Supported Reset Source: sys_por_rst_n |
| 5 | CLSTR28_CFG_SINGLE_CORE | R | 1h | Single / Dual CPU Mode: 0 = Unsupported on this device 1 = Only CPU0 is active. Reset Source: sys_por_rst_n |
| 4 | CLSTR28_CFG_MEM_INIT_DIS | R/W | 0h | Disables SRAM initialization (TCM, Cache Tags, etc) at reset Initialization must be performed for proper initial ECC initialization. The mem_init_dis value must be selected prior to R5 reset assertion. 1'b0 - Perform memory initialization 1'b1 - Disable memory initialization Reset Source: mod_g_rst_n |
| 3 | CLSTR28_CFG_LOCKSTEP_EN | R | 0h | Lockstep Not Supported Reset Source: sys_por_rst_n |
| 2 | CLSTR28_CFG_DBG_NO_CLKSTOP | R/W | 0h | CPU clockstop behavior 0 - CPU clocks stopped and nCLOCKSTOPPED asserted in standby mode 1 - CPU clocks not stopped in standby mode Reset Source: sys_por_rst_n |
| 1 | CLSTR28_CFG_TEINIT | R/W | 0h | Exception handling state at reset: 0 - ARM mode 1 - Thumb mode CAUTION: This bit must not be modified if R5F core has been released from reset. Reset Source: sys_por_rst_n |
| 0 | CLSTR28_CFG_LOCKSTEP | R | 0h | Lockstep Not Supported Reset Source: sys_por_rst_n |