SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
All timers include specific functions to generate accurate tick interrupts to the operating system.
Each timer can be clocked from several different independent clocks. The selection of clock source is made from the TIMERn_CLKSEL registers, where n is in the instance .
In the MCU domain the device provides up to 4 timer pins, one for each instance, to be used as MCU Timer Capture inputs or as MCU Timer PWM outputs. (See Module Integration and the device specific datasheet to see if MCU Timers apply)
In the MAIN domain the device provides up to 11 timer pins, one for each instance, to be used as Timer Capture inputs or as Timer PWM outputs. (See device specific datasheet to see details on timer pins.)
Each odd numbered timer instance from each of the domains may be optionally cascaded with the previous even numbered timer instance from the same domain to form up to a 64-bit timer. For example, TIMER1 may be cascaded to TIMER0, MCU_TIMER1 may be cascaded to MCU_TIMER0, etc.
When cascaded, TIMERi acts as a 32-bit prescaler to TIMERi+1, as well as MCU_TIMERn acts as a 32-bit prescaler to MCU_TIMERn+1. TIMERi / MCU_TIMERn must be configured to generate a PWM output edge at the desired rate to increment the TIMERi+1/ MCU_TIMERn+1 counter.
Figure 6-32 is an overview of the timers.