SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Contains the lower 32 bits of the boot vector location for R5 Core1. Bits 4:0 are not used and are always 0.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MAIN_SEC_MMR0 | 45A0 0190h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CLSTR0_CORE1_BOOTVECT_LO_VECT_ADDR | |||||||
| R/W | |||||||
| 4h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CLSTR0_CORE1_BOOTVECT_LO_VECT_ADDR | |||||||
| R/W | |||||||
| 4h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CLSTR0_CORE1_BOOTVECT_LO_VECT_ADDR | |||||||
| R/W | |||||||
| 4h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLSTR0_CORE1_BOOTVECT_LO_VECT_ADDR | RESERVED | ||||||
| R/W | NONE | ||||||
| 4h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:7 | CLSTR0_CORE1_BOOTVECT_LO_VECT_ADDR | R/W | 4h | Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0. Reset Source: sys_por_rst_n |
| 6:0 | RESERVED | NONE | 0h | Reserved |