The C7x CorePac implements a
hierarchical cache memory system with the following levels:
- Level 1 (L1):
- L1 program memory
controller (PMC) with associated L1 program memory (L1P)
- L1 data memory controller
(DMC) with associated L1 data memory (L1D)
- Level 2 (L2):
- L2 unified memory
controller (UMC) with associated L2 memory