The CorePac Memory Management Unit
(CMMU) extends the C7x architecture with support for address translation, access
permission and protections and memory attributes determination and checking. It is
implemented per C7x cluster as a two-level TLB structure. The CMMU works with the
C7x L1 caches, stream buffers in each processor and CorePac memory system of CorePac
cluster to translate virtual addresses to physical addresses, controls tablewalk
hardware that accesses translation tables in main memory. The CMMU enables
fine-grained memory system control through a set of virtual-to-physical address
mappings and memory attributes held in the L1 level micro translation look-aside
buffer (uTLB) and CorePac cluster level translation look-aside buffers (TLBs).
The CMMU provides the following key
features:
- Supports AArch32 LPAE and AArch64
page table format
- Programmable levels of
page table translation
- 4KB, 16KB, 64KB
translation granules
- Supports multiple page sizes:
4KB, 16KB, 64KB, 2MB, 32MB, 512MB, 1GB, 16GB
- Supports both hardware and
software managed table walks
- Hierarchical Table Lookaside
Buffer (TLB) caching page entries, intermediate page walk pointers for optimum
address translation performance
- Micro-TLB (uTLB) as first
level TLB
- 16-entry fully
associative dual interface L1 data uTLB
- 8-entry fully
associative L1 instruction uTLB
- CorePac (L2) TLB as
second level TLB
- 512-entry 4-way
associative TLB cache, caching both instruction and data page
translations with virtual-to-physical address mapping
- Intermediate
table walk caches to reduce memory access during multi-level
page walk
- Allows caching
and sharing of intermediate table walks and page tables in the
system cache hierarchy
- Security extensions that
facilitate the development of secure applications
- Soft-error protection on all RAM
and data storage structures