SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Selects the functional clock source for McASP1
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 A334h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | MCASP1_CLKSEL_LOC_AUXCLK_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MCASP1_CLKSEL_AUXCLK_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:10 | RESERVED | NONE | 0h | Reserved |
| 9:8 | MCASP1_CLKSEL_LOC_AUXCLK_SEL_PROXY | R/W | 0h | Selects the local clock source to use for McASP1 AUXCLK Field values (others are reserved): 2'b00 - PLL4_REF_CLK (as selected by MAIN_PLL4_CLKSEL_clk_sel) 2'b01 - PLL4_REF_CLK / 2 (as selected by MAIN_PLL4_CLKSEL_clk_sel) 2'b10 - MAIN_PLL4_HSDIV0_CLKOUT Reset Source: mod_g_rst_n |
| 7:3 | RESERVED | NONE | 0h | Reserved |
| 2:0 | MCASP1_CLKSEL_AUXCLK_SEL_PROXY | R/W | 0h | Selects the system AUXCLK input source for McASP1 Field values (others are reserved): 3'b000 - MAIN_PLL2_HSDIV8_CLKOUT 3'b001 - MAIN_PLL1_HSDIV6_CLKOUT 3'b011 - AUDIO_EXT_REFCLK0 (Pin) 3'b100 - AUDIO_EXT_REFCLK1 (Pin) 3'b101 - AUDIO_EXT_REFCLK2 (Pin) 3'b110 - ATCLK0 3'b111 - ATCLK1 Reset Source: mod_g_rst_n |