SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0014h |
| UART1 | 0281 0014h |
| UART2 | 0282 0014h |
| UART3 | 0283 0014h |
| UART4 | 0284 0014h |
| UART5 | 0285 0014h |
| UART6 | 0286 0014h |
| WKUP_UART0 | 2B30 0014h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| THR_EMPTY | STS_FIFO_FULL | RX_LAST_BYTE | FRAME_TOO_LONG | ABORT | CRC | STS_FIFO_E | RX_FIFO_E |
| R | R | R | R | R | R | R | R |
| 1h | 0h | 0h | 0h | 0h | 0h | 1h | 1h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | NONE | 0h | Reserved |
| 7 | THR_EMPTY | R | 1h | 0 Transmit holding register (TX FIFO) is not
empty
1 Transmit hold register (TX FIFO) is empty.
The transmission is not necessarily
completed |
| 6 | STS_FIFO_FULL | R | 0h | 0 Status FIFO not full 1 Status FIFO full |
| 5 | RX_LAST_BYTE | R | 0h | 0 The RX FIFO (RHR) does not contain the last
byte of the frame to be read
1 The RX FIFO (RHR) contains the last byte of
the frame to be read.This bit is only set
when the last byte of a frame is available
to be read. It is used to determine the
frame boundary. It is cleared on a single
read of the LSR register |
| 4 | FRAME_TOO_LONG | R | 0h | 0 No frame-too-long error in frame
1 Frame-too-long error in the frame at the
top of the STATUS FIFO, [next character to
be read]. This bit is set to 1 when a frame
exceeding the maximum length (set by RXFLH
and RXFLL registers) has been received.
When this error is detected, current frame
reception is terminated. Reception is
stopped until the next START flag is
detected |
| 3 | ABORT | R | 0h | 0 No abort pattern error in frame
1 Abort pattern is received. SIR & MIR:
Abort pattern. FIR: Illegal symbol |
| 2 | CRC | R | 0h | 0 No CRC error in frame
1 CRC error in the frame at the top of the
STATUS FIFO (next character to be read) |
| 1 | STS_FIFO_E | R | 1h | 0 Status FIFO not empty 1 Status FIFO empty |
| 0 | RX_FIFO_E | R | 1h | 0 No data in the receive FIFO 1 At least one data character in the RX FIFO |