SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Counter Compare Control Register
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| Instance Name | Physical Address |
|---|---|
| EPWM0 | 2300 000Eh |
| EPWM1 | 2301 000Eh |
| EPWM2 | 2302 000Eh |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | SHDWBFULL | SHDWAFULL | |||||
| R | R | R | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED2 | SHDWBMODE | RESERVED3 | SHDWAMODE | LOADBMODE | LOADAMODE | ||
| R | R/W | R | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:10 | RESERVED1 | R | 0h | Reserved |
| 9 | SHDWBFULL | R | 0h | Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs 0h CMPB shadow FIFO not full yet
1h Indicates the CMPB shadow FIFO is full. A
CPU write will overwrite current shadow
value. |
| 8 | SHDWAFULL | R | 0h | Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears once a load-strobe occurs 0h CMPA shadow FIFO not full yet
1h Indicates the CMPA shadow FIFO is full, a
CPU write will overwrite the current shadow
value |
| 7 | RESERVED2 | R | 0h | Reserved |
| 6 | SHDWBMODE | R/W | 0h | Counter-compare B [CMPB] Register Operating Mode 0h Shadow mode. Operates as a double buffer.
All writes via the CPU access the shadow
register.
1h Immediate mode. Only the active compare B
register is used. All writes and reads
directly access the active register for
immediate compare action. |
| 5 | RESERVED3 | R | 0h | Reserved |
| 4 | SHDWAMODE | R/W | 0h | Counter-compare A [CMPA] Register Operating Mode 0h Shadow mode. Operates as a double buffer.
All writes via the CPU access the shadow
register.
1h Immediate mode. Only the active compare
register is used. All writes and reads
directly access the active register for
immediate compare action. |
| 3:2 | LOADBMODE | R/W | 0h | Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1] 0h Load on EPWM_TBCNT[15-0] TBCNT =
0h Time-base counter equal to zero
(EPWM_TBCNT[15-0] TBCNT= 0000h)
1h Load on EPWM_TBCNT[15-0] TBCNT =
EPWM_TBPRD[15-0] TBPRD: Time-base counter
equal to period (EPWM_TBCNT[15-0] TBCNT =
EPWM_TBPRD[15-0] TBPRD)
2h Load on either EPWM_TBCNT[15-0] TBCNT = 0
or EPWM_TBCNT[15-0] TBCNT =
EPWM_TBPRD[15-0] TBPRD
3h Freeze (no loads possible) |
| 1:0 | LOADAMODE | R/W | 0h | Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1] 0h Load on TBCNT =
0h Time-base counter equal to zero
(EPWM_TBCNT[15-0] TBCNT = 0000h)
1h Load on TBCNT = TBPRD: Time-base counter
equal to period (EPWM_TBCNT[15-0] TBCNT=
EPWM_TBPRD[15-0] TBPRD)
2h Load on either EPWM_TBCNT[15-0] TBCNT = 0h
3h Freeze (no loads possible) |