SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Selects the AHCLKX and AHCLKR clock source for McASP1
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 8354h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | MCASP1_AHCLKSEL_AHCLKX_SEL | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MCASP1_AHCLKSEL_AHCLKR_SEL | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:12 | RESERVED | NONE | 0h | Reserved |
| 11:8 | MCASP1_AHCLKSEL_AHCLKX_SEL | R/W | 0h | Selects the AHCLKX input source for McASP1 Field values (others are reserved): 4'b0000 - EXT_REFCLK1 (Pin) 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0 (Pin) 4'b0011 - AUDIO_EXT_REFCLK1 (Pin) 4'b0100 - AUDIO_EXT_REFCLK2 (Pin) undefined - undefined 4'b0110 - MLB_IO_CLK undefined - undefined 4'b1000 - ATCLK0 4'b1001 - ATCLK1 4'b1010 - ATCLK2 4'b1011 - ATCLK3 4'b1100 - CPSW CPTS GENF0 4'b1101 - CPSW CPTS GENF0 Reset Source: mod_g_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | MCASP1_AHCLKSEL_AHCLKR_SEL | R/W | 0h | Selects the AHCLKR input source for McASP1 Field values (others are reserved): 4'b0000 - EXT_REFCLK1 (Pin) 4'b0001 - HFOSC0_CLKOUT 4'b0010 - AUDIO_EXT_REFCLK0 (Pin) 4'b0011 - AUDIO_EXT_REFCLK1 (Pin) 4'b0100 - AUDIO_EXT_REFCLK2 (Pin) undefined - undefined 4'b0110 - MLB_IO_CLK undefined - undefined 4'b1000 - ATCLK0 4'b1001 - ATCLK1 4'b1010 - ATCLK2 4'b1011 - ATCLK3 4'b1100 - CPSW CPTS GENF0 4'b1101 - CPSW CPTS GENF0 Reset Source: mod_g_rst_n |