SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Counter/Timer Ownership register 28
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 8AF0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| OWNERSHIP | DBG_OVERIDE | CURRENT_OWNER | RESERVED | ||||
| R/W | R/W | R | R | ||||
| 0h | 1h | 0h | 0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | OWNERSHIP | R/W | 0h | Counter/Timer Ownership Status. The Read encoding is (0=Available, 1=Claimed, 2=Enabled, 3=Reserved). The write commands are (0=release, 1=claim, 2=enable, 3=nop) |
| 29 | DBG_OVERIDE | R/W | 1h | This bit indicates the debugger is Claiming the resource, always reads back as 1 |
| 28 | CURRENT_OWNER | R | 0h | This value reflects the Counter/Timer ownership when the register is in a non-Available state, 1=Ap owned, 0=Dbg owned |
| 27:0 | RESERVED | R | 0h | Reserved, returns 0 |