SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way. This register is only used when the tx_chan_type is configured as a Third Party DMA channel. This register has no function when the channel is configured for packet mode transfers. A write to this register will cause an event to be sent to this channel.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| DMASS0_BCDMA_0 | 4A84 0008h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TRIGGER | ||||||
| NONE | NA/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | RESERVED | NONE | 0h | Reserved |
| 0 | TRIGGER | NA/W | 0h | Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel Reset Source: rst_mod_g_rst_n |