SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Enables and selects clock source of WKUP_CLKOUT pin
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4300 A020h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | CLKOUT_CTRL_OUT_MUX_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CLKOUT_CTRL_WKUP_CLKOUT_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24 | CLKOUT_CTRL_OUT_MUX_SEL_PROXY | R/W | 0h | WKUP CLKOUT (Pin) pin output mux selection. HFOSC0_CLK is a direct output from the HFOSC0 Field values (others are reserved): 1'b0 - CLK_DIV_OUT 1'b1 - HFOSC0_CLK (clk_sel must be DRIVE_LOW) Reset Source: mod_por_rst_n |
| 23:3 | RESERVED | NONE | 0h | Reserved |
| 2:0 | CLKOUT_CTRL_WKUP_CLKOUT_SEL_PROXY | R/W | 0h | Controls WKUP CLKOUT MUX for WKUP_CLKOUT0 Pin Field values (others are reserved): 3'b000 - HFOSC0_CLKOUT_SERDES 3'b000 - DRIVE_LOW 3'b001 - LFOSC0_CLKOUT 3'b010 - MAIN_PLL0_HSDIV2_CLKOUT 3'b011 - MAIN_PLL1_HSDIV2_CLKOUT 3'b100 - MAIN_PLL2_HSDIV9_CLKOUT 3'b101 - DEVICE_CLKOUT_32K 3'b110 - CLK_12M_RC 3'b111 - HFOSC0_CLKOUT Reset Source: mod_por_rst_n |