SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
SPI2 clock control
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 A208h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SPI2_CLKSEL_MSTR_LB_CLKSEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:17 | RESERVED | NONE | 0h | Reserved |
| 16 | SPI2_CLKSEL_MSTR_LB_CLKSEL_PROXY | R/W | 0h | Controller mode receive capture clock loopback selection Field values (others are reserved): 1'b0 - INTERNAL_LOOPBACK 1'b1 - EXTERNAL_LOOPBACK Reset Source: mod_g_rst_n |
| 15:0 | RESERVED | NONE | 0h | Reserved |