SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Register for overriding various Controller interrupts for easy activation during DV. NOTE: This is only for internal purposes and should NOT be used during functional operation.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0F90 0490h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | HOST_SYSTEM_ERR_TEST | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IRQ_TEST | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:9 | RESERVED | NONE | 0h | Reserved |
| 8 | HOST_SYSTEM_ERR_TEST | R/W | 0h | Test for host system error interrupt. Set 1 to cause host_system_error_intr to trigger and clear this bit to clear the interrupt condition. Reset Source: cfg_srst_n |
| 7:0 | IRQ_TEST | R/W | 0h | Test for irq interrupts from core. Each bit sets corresponding irq_intr bit. Set 1 to each bit based on whether that interrupt needs to trigger and clear the bit in ISR to clear interrupt condition. Reset Source: cfg_srst_n |