SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Counter Timer Counter Register 23
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_DEBUG | 0007 3800 8BDCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| COUNT | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| COUNT | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| COUNT | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COUNT | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | COUNT | R | 0h | This field reflects the current value of the counter. It is incremented when the system events configured in the corresponding Counter Control Register is asserted. If CTCRn.CHNSHD is set, the Counter will increment when the low order counter rolls over. |