SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Status bits showing the PULSAR CPU1 EVNT_BUS single bit error counters
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| Instance Name | Physical Address |
|---|---|
| R5FSS0_COMMON0 | 05B0 1008h |
| R5FSS1_COMMON0 | 05B2 1008h |
| WKUP_R5FSS0_COMMON0 | 3C01 8008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | EVNT_BUS8 | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EVNT_BUS7 | EVNT_BUS6 | EVNT_BUS5 | EVNT_BUS4 | ||||
| R | R | R | R | ||||
| 0h | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EVNT_BUS3 | EVNT_BUS2 | EVNT_BUS1 | EVNT_BUS0 | ||||
| R | R | R | R | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:18 | RESERVED | NONE | 0h | Reserved |
| 17:16 | EVNT_BUS8 | R | 0h | Status bits showing the PULSAR CPU1 EVNT 8 single bit error counter. Reset Source: mod_g_rst_n |
| 15:14 | EVNT_BUS7 | R | 0h | Status bits showing the PULSAR CPU1 EVNT 7 single bit error counter. Reset Source: mod_g_rst_n |
| 13:12 | EVNT_BUS6 | R | 0h | Status bits showing the PULSAR CPU1 EVNT 6 single bit error counter. Reset Source: mod_g_rst_n |
| 11:10 | EVNT_BUS5 | R | 0h | Status bits showing the PULSAR CPU1 EVNT 5 single bit error counter. Reset Source: mod_g_rst_n |
| 9:8 | EVNT_BUS4 | R | 0h | Status bits showing the PULSAR CPU1 EVNT 4 single bit error counter. Reset Source: mod_g_rst_n |
| 7:6 | EVNT_BUS3 | R | 0h | Status bits showing the PULSAR CPU1 EVNT 3 single bit error counter. Reset Source: mod_g_rst_n |
| 5:4 | EVNT_BUS2 | R | 0h | Status bits showing the PULSAR CPU1 EVNT 2 single bit error counter. Reset Source: mod_g_rst_n |
| 3:2 | EVNT_BUS1 | R | 0h | Status bits showing the PULSAR CPU1 EVNT 1 single bit error counter. Reset Source: mod_g_rst_n |
| 1:0 | EVNT_BUS0 | R | 0h | Status bits showing the PULSAR CPU1 EVNT 0 single bit error counter. Reset Source: mod_g_rst_n |