SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| Step | Register/Bit Field/Programming Model | Value |
|---|---|---|
| Enable interrupt event | MAILBOX_IRQ_ENABLE_SET_j[0 + y*2] | 0x1 |
| User (processor) can perform another task until interrupt occurs See Section 8.2.3.1.3.2 for interrupt handling in receiving mode |