SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register controls which internal clock is made observable on the OBSCLK0/1 output pins
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 A000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | OBSCLK0_CTRL_OUT_MUX_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | OBSCLK0_CTRL_CLK_DIV_LD_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| OBSCLK0_CTRL_CLK_DIV_PROXY | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | OBSCLK0_CTRL_CLK_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 7h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24 | OBSCLK0_CTRL_OUT_MUX_SEL_PROXY | R/W | 0h | OBSCLK pin output mux selection. PLL4_REFCLK is the direct output from either HFOSC0 or HFOSC1. Field values (others are reserved): 1'b0 - Selects the output of the CLK_DIV_OUT clock mux 1'b1 - Select PLL4_REFCLK (clk_sel value must be 5'b11111) Reset Source: mod_por_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | OBSCLK0_CTRL_CLK_DIV_LD_PROXY | R/W | 0h | Load divisor value from clk_div field, when the bit is toggled from 0 to 1. Field values (others are reserved): 1'b0 - READY 1'b1 - LOAD Reset Source: mod_por_rst_n |
| 15:8 | OBSCLK0_CTRL_CLK_DIV_PROXY | R/W | 0h | OBSCLK0 output divider. Sets divider to divide by clkdiv + 1. Divide by 1 to 256 are supported. After Writing to this field, the clk_div_ld field must be toggled. Reset Source: mod_por_rst_n |
| 7:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | OBSCLK0_CTRL_CLK_SEL_PROXY | R/W | 7h | OBSCLK0 clock source selection. Selects the source of the clock to be divided by the OBSCLK0 divider. Field values (others are reserved): 5'b00000 - MAIN_PLL0_HSDIV0_CLKOUT 5'b00001 - MAIN_PLL1_HSDIV0_CLKOUT 5'b00010 - MAIN_PLL2_HSDIV0_CLKOUT 5'b00011 - MAIN_PLL4_HSDIV0_CLKOUT 5'b00100 - MAIN_PLL14_HSDIV0_CLKOUT 5'b00101 - CLK_12M_RC 5'b00110 - HFOSC0_CLKOUT_32K 5'b00111 - PLLCTRL_OBSCLK 5'b01000 - HFOSC0_CLKOUT 5'b01001 - CLK_32K_RC 5'b01010 - CPSW0_CPTS_GENF0 5'b01011 - CPSW0_CPTS_GENF1 5'b01100 - MCU_PLL0_HSDIV0_CLKOUT 5'b01101 - MAIN_PLL15_HSDIV0_CLKOUT undefined - undefined undefined - undefined undefined - undefined 5'b10000 - MAIN_SYSCLK0 5'b10001 - DEVICE_CLKOUT_32K undefined - undefined 5'b10011 - C7XV_CLK_DIV4 undefined - undefined undefined - undefined 5'b11111 - OFF (Must Select this option when out_mux_sel is set to PLL4_REFCLK) Reset Source: mod_por_rst_n |