Single or Dual Core DSP C7x256V (DSP C7x) Subsystem has the following features:
- C7x ISA and RISC-V G ISA extensions
- Vector DSP, 40 GFLOPS
- 256-bit vector width
- L1 memory architecture
- 32KB I-cache
- 64KB D-cache
- L2 memory architecture
- Repurposing of L2/EL2 embedded memory for use by SOC resources when C7x/MMA/DRU are disabled
- 2.25MB L2 with ECC protection on L2 SRAM which is managed as 2MB segment named "Main" and 256KB segment named "Auxiliary". A continuous L2 memory view via tie off.
- Unified Memory Controller (UMC) facilitates L2 SRAM accesses from CPU and SOC (DMAs) as well as EMIF accesses from CPU.
- Full ECC Support with RMW
- DRU (DMA engine) integrated that facilitates data transfer between L2, VPAC and EMIF.
- Event bus interface integrates with SOC DMSS
- Tightly coupled with C7x/MMA (DRU is not available for use when the C7x/MMA is disabled)
- Interrupts
- Local event controller (CLEC) integrated within CorePac for routing and handling of DRU interrupts, CPU generated IPC events to SOC, interrupts coming from SOC
- Security
- Support for C7x Authenticated Boot. Security is in-context during boot to facilitate the authentication and loading of the C7x image. (per approved CR: PROC_SOC-4890 )
- C7x native security level (TrustZone equivalent) is not supported on the device, and the core executes code in non-secure state of C7x. The secure sideband signal (output) from the C7x data plane initiator interface can be left floating.
- The C7x L2 SRAM (UMC) can not be used for storing security content as there is no protection of UMC memory from C7x. In a threat scenario, the C7x can be activated if in reset to execute malicious code to access data in UMC thereby defeating a protection for security data in UMC.
- No security can be inferred from DRU as this IP is out of scope for security.
- TrustZone debug controls (DBGEN, NIDEN, SPIDEN, SPNIDEN) are supported
- Safety
- Support for reporting safety errors to SOC via interrupt
- Debug
- Independent debug interface supporting access to embedded features
- Debug features include: Core debug, Advanced Event Triggering, Trace, CTSETs, and an embedded CP Tracer Aggregator with bus probes on internal memory interfaces
- Power Management
- Support for granular gated clock domains to support low power modes and to support memory interface utilization while IP disabled.
- Dedicated PLL for full flexibility in performance and power trade-offs
- Dedicated windowed watchdog timer per core
- DSP0 C7x supports Deep-learning Matrix Multiply Accelerator (MMA2F) with floating support