SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| IN Interrupt | Connected To |
|---|---|
|
C7X256V0_CLEC_GIC_SPI_IN_32 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_33 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_1 |
|
C7X256V0_CLEC_GIC_SPI_IN_34 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_2 |
|
C7X256V0_CLEC_GIC_SPI_IN_35 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_3 |
|
C7X256V0_CLEC_GIC_SPI_IN_36 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_4 |
|
C7X256V0_CLEC_GIC_SPI_IN_37 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_5 |
|
C7X256V0_CLEC_GIC_SPI_IN_38 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_6 |
|
C7X256V0_CLEC_GIC_SPI_IN_39 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_7 |
|
C7X256V0_CLEC_GIC_SPI_IN_40 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_8 |
|
C7X256V0_CLEC_GIC_SPI_IN_41 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_9 |
|
C7X256V0_CLEC_GIC_SPI_IN_42 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_10 |
|
C7X256V0_CLEC_GIC_SPI_IN_43 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_11 |
|
C7X256V0_CLEC_GIC_SPI_IN_44 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_12 |
|
C7X256V0_CLEC_GIC_SPI_IN_45 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_13 |
|
C7X256V0_CLEC_GIC_SPI_IN_46 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_14 |
|
C7X256V0_CLEC_GIC_SPI_IN_47 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_15 |
|
C7X256V0_CLEC_GIC_SPI_IN_48 |
CPSW0_CPTS_COMP_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_50 |
AASRC0_INFIFO_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_51 |
AASRC0_INGROUP_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_52 |
AASRC0_OUTFIFO_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_53 |
AASRC0_OUTGROUP_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_54 |
AASRC0_ERR_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_55 |
AASRC1_INFIFO_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_56 |
AASRC1_INGROUP_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_57 |
AASRC1_OUTFIFO_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_58 |
AASRC1_OUTGROUP_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_59 |
AASRC1_ERR_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_60 |
MLB0_MLBSS_MLB_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_61 |
MLB0_MLBSS_MLB_AHB_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_62 |
MLB0_MLBSS_MLB_AHB_INT_OUT_1 |
|
C7X256V0_CLEC_GIC_SPI_IN_64 |
TIMER8_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_65 |
TIMER9_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_66 |
TIMER10_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_67 |
TIMER11_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_68 |
TIMER12_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_69 |
TIMER13_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_70 |
TIMER14_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_71 |
TIMER15_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_96 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_32 |
|
C7X256V0_CLEC_GIC_SPI_IN_97 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_33 |
|
C7X256V0_CLEC_GIC_SPI_IN_98 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_34 |
|
C7X256V0_CLEC_GIC_SPI_IN_99 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_35 |
|
C7X256V0_CLEC_GIC_SPI_IN_100 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_36 |
|
C7X256V0_CLEC_GIC_SPI_IN_101 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_37 |
|
C7X256V0_CLEC_GIC_SPI_IN_102 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_38 |
|
C7X256V0_CLEC_GIC_SPI_IN_103 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_39 |
|
C7X256V0_CLEC_GIC_SPI_IN_104 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_105 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_1 |
|
C7X256V0_CLEC_GIC_SPI_IN_106 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_2 |
|
C7X256V0_CLEC_GIC_SPI_IN_107 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_3 |
|
C7X256V0_CLEC_GIC_SPI_IN_112 |
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_4 |
|
C7X256V0_CLEC_GIC_SPI_IN_113 |
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_5 |
|
C7X256V0_CLEC_GIC_SPI_IN_128 |
DCC0_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_128 |
DCC1_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_128 |
DCC2_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_128 |
DCC3_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_128 |
DCC4_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_128 |
DCC5_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_128 |
DCC6_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_128 |
DCC7_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_128 |
DCC8_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_129 |
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_129 |
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_129 |
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_129 |
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_129 |
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_131 |
EFUSE0_EFC_ERROR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_132 |
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_133 |
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_133 |
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_133 |
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_133 |
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_133 |
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_133 |
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_133 |
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_133 |
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_133 |
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_133 |
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_134 |
CPSW0_EVNT_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_135 |
CPSW0_MDIO_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_136 |
CPSW0_STAT_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_145 |
ECAP0_ECAP_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_146 |
ECAP1_ECAP_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_147 |
ECAP2_ECAP_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_148 |
ECAP3_ECAP_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_149 |
ECAP4_ECAP_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_150 |
ECAP5_ECAP_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_151 |
ADC0_GEN_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_152 |
TIMER0_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_153 |
TIMER1_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_154 |
TIMER2_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_155 |
TIMER3_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_156 |
TIMER4_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_157 |
TIMER5_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_158 |
TIMER6_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_159 |
TIMER7_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_160 |
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_161 |
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_165 |
MMCSD0_EMMCSDSS_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_166 |
MCRC64_0_INT_MCRC_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_169 |
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_170 |
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_171 |
FSS0_OSPI0_LVL_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_172 |
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_173 |
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_174 |
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_175 |
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_177 |
DDPA0_DDPA_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_178 |
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_179 |
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_180 |
ESM0_ESM_INT_CFG_LVL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_181 |
ESM0_ESM_INT_HI_LVL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_182 |
ESM0_ESM_INT_LOW_LVL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_183 |
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_184 |
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_185 |
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_186 |
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_187 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_188 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
|
C7X256V0_CLEC_GIC_SPI_IN_189 |
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_190 |
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_191 |
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_193 |
I2C0_POINTRPEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_194 |
I2C1_POINTRPEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_195 |
I2C2_POINTRPEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_196 |
I2C3_POINTRPEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_197 |
WKUP_I2C0_POINTRPEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_199 |
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_201 |
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_202 |
DEBUGSS0_CTM_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_203 |
MAIN_PSC0_PSC_ALLINT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_204 |
MCSPI0_INTR_SPI_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_205 |
MCSPI1_INTR_SPI_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_206 |
MCSPI2_INTR_SPI_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_207 |
MCSPI3_INTR_SPI_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_208 |
MCSPI4_INTR_SPI_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_210 |
UART0_USART_IRQ_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_211 |
UART1_USART_IRQ_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_212 |
UART2_USART_IRQ_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_213 |
UART3_USART_IRQ_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_214 |
UART4_USART_IRQ_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_215 |
UART5_USART_IRQ_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_216 |
UART6_USART_IRQ_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_218 |
WKUP_UART0_USART_IRQ_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_220 |
USB0_IRQ_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_221 |
USB0_IRQ_OUT_1 |
|
C7X256V0_CLEC_GIC_SPI_IN_222 |
USB0_IRQ_OUT_2 |
|
C7X256V0_CLEC_GIC_SPI_IN_223 |
USB0_IRQ_OUT_3 |
|
C7X256V0_CLEC_GIC_SPI_IN_224 |
USB0_IRQ_OUT_4 |
|
C7X256V0_CLEC_GIC_SPI_IN_225 |
USB0_IRQ_OUT_5 |
|
C7X256V0_CLEC_GIC_SPI_IN_226 |
USB0_IRQ_OUT_6 |
|
C7X256V0_CLEC_GIC_SPI_IN_227 |
USB0_IRQ_OUT_7 |
|
C7X256V0_CLEC_GIC_SPI_IN_228 |
USB0_MISC_LEVEL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_229 |
EPWM0_EPWM_ETINT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_230 |
EPWM0_EPWM_TRIPZINT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_231 |
EPWM1_EPWM_ETINT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_233 |
EPWM1_EPWM_TRIPZINT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_234 |
EPWM2_EPWM_ETINT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_235 |
EPWM2_EPWM_TRIPZINT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_245 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_246 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
|
C7X256V0_CLEC_GIC_SPI_IN_247 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_248 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
|
C7X256V0_CLEC_GIC_SPI_IN_249 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_250 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
|
C7X256V0_CLEC_GIC_SPI_IN_251 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_252 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
|
C7X256V0_CLEC_GIC_SPI_IN_256 |
PINFUNCTION_EXTINTNIN_EXTINTN_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_261 |
RL2_0_ERR_LVL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_262 |
RL2_2_ERR_LVL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_263 |
RL2_3_ERR_LVL_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_267 |
MCASP0_REC_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_268 |
MCASP0_XMIT_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_269 |
MCASP1_REC_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_270 |
MCASP1_XMIT_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_271 |
MCASP2_REC_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_272 |
MCASP2_XMIT_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_273 |
MCASP3_REC_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_274 |
MCASP3_XMIT_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_275 |
MCASP4_REC_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_GIC_SPI_IN_276 |
MCASP4_XMIT_INTR_PEND_OUT_0 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_4 |
RTI4_INTR_WWD_OUT_0 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_5 |
MAIN_CTRL_MMR0_IPC_SET0_IPC_SET_IPCFG_OUT_0 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_6 |
MAILBOX0_MAILBOX_CLUSTER_1_MAILBOX_CLUSTER_PEND_OUT_2 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_7 |
MAILBOX0_MAILBOX_CLUSTER_2_MAILBOX_CLUSTER_PEND_OUT_2 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_8 |
MAILBOX0_MAILBOX_CLUSTER_3_MAILBOX_CLUSTER_PEND_OUT_2 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_9 |
MAILBOX0_MAILBOX_CLUSTER_4_MAILBOX_CLUSTER_PEND_OUT_2 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_10 |
MAILBOX0_MAILBOX_CLUSTER_7_MAILBOX_CLUSTER_PEND_OUT_1 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_12 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_20 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_13 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_21 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_14 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_22 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_15 |
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_23 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_16 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_84 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_17 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_85 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_18 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_86 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_19 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_87 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_20 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_88 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_21 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_89 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_22 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_90 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_23 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_91 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_24 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_92 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_25 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_93 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_26 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_94 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_27 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_95 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_28 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_96 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_29 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_97 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_30 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_98 |
|
C7X256V0_CLEC_SOC_EVENTS_IN_IN_31 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_99 |
|
C7X256V1_CLEC_GIC_SPI_IN_32 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_33 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_1 |
|
C7X256V1_CLEC_GIC_SPI_IN_34 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_2 |
|
C7X256V1_CLEC_GIC_SPI_IN_35 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_3 |
|
C7X256V1_CLEC_GIC_SPI_IN_36 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_4 |
|
C7X256V1_CLEC_GIC_SPI_IN_37 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_5 |
|
C7X256V1_CLEC_GIC_SPI_IN_38 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_6 |
|
C7X256V1_CLEC_GIC_SPI_IN_39 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_7 |
|
C7X256V1_CLEC_GIC_SPI_IN_40 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_8 |
|
C7X256V1_CLEC_GIC_SPI_IN_41 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_9 |
|
C7X256V1_CLEC_GIC_SPI_IN_42 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_10 |
|
C7X256V1_CLEC_GIC_SPI_IN_43 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_11 |
|
C7X256V1_CLEC_GIC_SPI_IN_44 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_12 |
|
C7X256V1_CLEC_GIC_SPI_IN_45 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_13 |
|
C7X256V1_CLEC_GIC_SPI_IN_46 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_14 |
|
C7X256V1_CLEC_GIC_SPI_IN_47 |
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_15 |
|
C7X256V1_CLEC_GIC_SPI_IN_48 |
CPSW0_CPTS_COMP_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_50 |
AASRC0_INFIFO_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_51 |
AASRC0_INGROUP_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_52 |
AASRC0_OUTFIFO_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_53 |
AASRC0_OUTGROUP_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_54 |
AASRC0_ERR_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_55 |
AASRC1_INFIFO_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_56 |
AASRC1_INGROUP_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_57 |
AASRC1_OUTFIFO_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_58 |
AASRC1_OUTGROUP_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_59 |
AASRC1_ERR_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_60 |
MLB0_MLBSS_MLB_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_61 |
MLB0_MLBSS_MLB_AHB_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_62 |
MLB0_MLBSS_MLB_AHB_INT_OUT_1 |
|
C7X256V1_CLEC_GIC_SPI_IN_64 |
TIMER8_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_65 |
TIMER9_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_66 |
TIMER10_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_67 |
TIMER11_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_68 |
TIMER12_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_69 |
TIMER13_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_70 |
TIMER14_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_71 |
TIMER15_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_96 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_32 |
|
C7X256V1_CLEC_GIC_SPI_IN_97 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_33 |
|
C7X256V1_CLEC_GIC_SPI_IN_98 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_34 |
|
C7X256V1_CLEC_GIC_SPI_IN_99 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_35 |
|
C7X256V1_CLEC_GIC_SPI_IN_100 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_36 |
|
C7X256V1_CLEC_GIC_SPI_IN_101 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_37 |
|
C7X256V1_CLEC_GIC_SPI_IN_102 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_38 |
|
C7X256V1_CLEC_GIC_SPI_IN_103 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_39 |
|
C7X256V1_CLEC_GIC_SPI_IN_104 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_105 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_1 |
|
C7X256V1_CLEC_GIC_SPI_IN_106 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_2 |
|
C7X256V1_CLEC_GIC_SPI_IN_107 |
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_3 |
|
C7X256V1_CLEC_GIC_SPI_IN_112 |
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_4 |
|
C7X256V1_CLEC_GIC_SPI_IN_113 |
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_5 |
|
C7X256V1_CLEC_GIC_SPI_IN_128 |
DCC0_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_128 |
DCC1_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_128 |
DCC2_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_128 |
DCC3_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_128 |
DCC4_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_128 |
DCC5_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_128 |
DCC6_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_128 |
DCC7_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_128 |
DCC8_INTR_DONE_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_129 |
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_129 |
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_129 |
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_129 |
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_129 |
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_131 |
EFUSE0_EFC_ERROR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_132 |
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_133 |
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_133 |
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_133 |
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_133 |
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_133 |
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_133 |
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_133 |
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_133 |
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_133 |
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_133 |
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_134 |
CPSW0_EVNT_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_135 |
CPSW0_MDIO_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_136 |
CPSW0_STAT_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_145 |
ECAP0_ECAP_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_146 |
ECAP1_ECAP_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_147 |
ECAP2_ECAP_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_148 |
ECAP3_ECAP_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_149 |
ECAP4_ECAP_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_150 |
ECAP5_ECAP_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_151 |
ADC0_GEN_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_152 |
TIMER0_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_153 |
TIMER1_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_154 |
TIMER2_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_155 |
TIMER3_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_156 |
TIMER4_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_157 |
TIMER5_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_158 |
TIMER6_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_159 |
TIMER7_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_160 |
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_161 |
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_165 |
MMCSD0_EMMCSDSS_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_166 |
MCRC64_0_INT_MCRC_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_169 |
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_170 |
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_171 |
FSS0_OSPI0_LVL_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_172 |
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_173 |
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_174 |
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_175 |
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_177 |
DDPA0_DDPA_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_178 |
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_179 |
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_180 |
ESM0_ESM_INT_CFG_LVL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_181 |
ESM0_ESM_INT_HI_LVL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_182 |
ESM0_ESM_INT_LOW_LVL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_183 |
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_184 |
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_185 |
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_186 |
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_187 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_188 |
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
|
C7X256V1_CLEC_GIC_SPI_IN_189 |
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_190 |
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_191 |
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_193 |
I2C0_POINTRPEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_194 |
I2C1_POINTRPEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_195 |
I2C2_POINTRPEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_196 |
I2C3_POINTRPEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_197 |
WKUP_I2C0_POINTRPEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_199 |
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_201 |
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_202 |
DEBUGSS0_CTM_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_203 |
MAIN_PSC0_PSC_ALLINT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_204 |
MCSPI0_INTR_SPI_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_205 |
MCSPI1_INTR_SPI_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_206 |
MCSPI2_INTR_SPI_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_207 |
MCSPI3_INTR_SPI_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_208 |
MCSPI4_INTR_SPI_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_210 |
UART0_USART_IRQ_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_211 |
UART1_USART_IRQ_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_212 |
UART2_USART_IRQ_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_213 |
UART3_USART_IRQ_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_214 |
UART4_USART_IRQ_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_215 |
UART5_USART_IRQ_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_216 |
UART6_USART_IRQ_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_218 |
WKUP_UART0_USART_IRQ_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_220 |
USB0_IRQ_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_221 |
USB0_IRQ_OUT_1 |
|
C7X256V1_CLEC_GIC_SPI_IN_222 |
USB0_IRQ_OUT_2 |
|
C7X256V1_CLEC_GIC_SPI_IN_223 |
USB0_IRQ_OUT_3 |
|
C7X256V1_CLEC_GIC_SPI_IN_224 |
USB0_IRQ_OUT_4 |
|
C7X256V1_CLEC_GIC_SPI_IN_225 |
USB0_IRQ_OUT_5 |
|
C7X256V1_CLEC_GIC_SPI_IN_226 |
USB0_IRQ_OUT_6 |
|
C7X256V1_CLEC_GIC_SPI_IN_227 |
USB0_IRQ_OUT_7 |
|
C7X256V1_CLEC_GIC_SPI_IN_228 |
USB0_MISC_LEVEL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_229 |
EPWM0_EPWM_ETINT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_230 |
EPWM0_EPWM_TRIPZINT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_231 |
EPWM1_EPWM_ETINT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_233 |
EPWM1_EPWM_TRIPZINT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_234 |
EPWM2_EPWM_ETINT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_235 |
EPWM2_EPWM_TRIPZINT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_245 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_246 |
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
|
C7X256V1_CLEC_GIC_SPI_IN_247 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_248 |
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
|
C7X256V1_CLEC_GIC_SPI_IN_249 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_250 |
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
|
C7X256V1_CLEC_GIC_SPI_IN_251 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_252 |
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
|
C7X256V1_CLEC_GIC_SPI_IN_256 |
PINFUNCTION_EXTINTNIN_EXTINTN_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_261 |
RL2_0_ERR_LVL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_262 |
RL2_2_ERR_LVL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_263 |
RL2_3_ERR_LVL_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_267 |
MCASP0_REC_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_268 |
MCASP0_XMIT_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_269 |
MCASP1_REC_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_270 |
MCASP1_XMIT_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_271 |
MCASP2_REC_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_272 |
MCASP2_XMIT_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_273 |
MCASP3_REC_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_274 |
MCASP3_XMIT_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_275 |
MCASP4_REC_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_GIC_SPI_IN_276 |
MCASP4_XMIT_INTR_PEND_OUT_0 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_4 |
RTI5_INTR_WWD_OUT_0 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_5 |
MAIN_CTRL_MMR0_IPC_SET1_IPC_SET_IPCFG_OUT_0 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_6 |
MAILBOX0_MAILBOX_CLUSTER_1_MAILBOX_CLUSTER_PEND_OUT_3 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_7 |
MAILBOX0_MAILBOX_CLUSTER_2_MAILBOX_CLUSTER_PEND_OUT_3 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_8 |
MAILBOX0_MAILBOX_CLUSTER_3_MAILBOX_CLUSTER_PEND_OUT_3 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_9 |
MAILBOX0_MAILBOX_CLUSTER_4_MAILBOX_CLUSTER_PEND_OUT_3 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_10 |
MAILBOX0_MAILBOX_CLUSTER_7_MAILBOX_CLUSTER_PEND_OUT_2 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_12 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_20 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_13 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_21 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_14 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_22 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_15 |
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_23 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_16 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_100 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_17 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_101 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_18 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_102 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_19 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_103 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_20 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_104 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_21 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_105 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_22 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_106 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_23 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_107 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_24 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_108 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_25 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_109 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_26 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_110 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_27 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_111 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_28 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_112 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_29 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_113 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_30 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_114 |
|
C7X256V1_CLEC_SOC_EVENTS_IN_IN_31 |
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_115 |
| OUT Interrupt | Connected To |
|---|---|
|
C7X256V0_CLEC_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE0_INTR_IN_113 |
|
C7X256V0_CLEC_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE1_INTR_IN_113 |
|
C7X256V0_CLEC_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE0_INTR_IN_113 |
|
C7X256V0_CLEC_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE1_INTR_IN_113 |
|
C7X256V0_CLEC_DFT_PBIST_CPU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_113 |
|
C7X256V0_CLEC_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_226 |
|
C7X256V0_CLEC_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_226 |
|
C7X256V0_CLEC_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_226 |
|
C7X256V0_CLEC_DFT_PBIST_SAFETY_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_149 |
|
C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_160 |
|
C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_1 |
ESM0_ESM_LVL_EVENT_IN_161 |
|
C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_2 |
ESM0_ESM_LVL_EVENT_IN_162 |
|
C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_3 |
ESM0_ESM_LVL_EVENT_IN_163 |
|
C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_4 |
ESM0_ESM_LVL_EVENT_IN_164 |
|
C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_5 |
ESM0_ESM_LVL_EVENT_IN_165 |
|
C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_6 |
ESM0_ESM_LVL_EVENT_IN_166 |
|
C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_7 |
ESM0_ESM_LVL_EVENT_IN_167 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_248 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_248 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_1 |
R5FSS0_CORE0_INTR_IN_249 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_1 |
R5FSS0_CORE1_INTR_IN_249 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_2 |
R5FSS0_CORE0_INTR_IN_250 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_2 |
R5FSS0_CORE1_INTR_IN_250 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_3 |
R5FSS0_CORE0_INTR_IN_251 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_3 |
R5FSS0_CORE1_INTR_IN_251 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_4 |
R5FSS0_CORE0_INTR_IN_252 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_4 |
R5FSS0_CORE1_INTR_IN_252 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_5 |
R5FSS0_CORE0_INTR_IN_253 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_5 |
R5FSS0_CORE1_INTR_IN_253 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_6 |
R5FSS0_CORE0_INTR_IN_254 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_6 |
R5FSS0_CORE1_INTR_IN_254 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_7 |
R5FSS0_CORE0_INTR_IN_255 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_7 |
R5FSS0_CORE1_INTR_IN_255 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_8 |
R5FSS1_CORE0_INTR_IN_248 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_8 |
R5FSS1_CORE1_INTR_IN_248 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_9 |
R5FSS1_CORE0_INTR_IN_249 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_9 |
R5FSS1_CORE1_INTR_IN_249 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_10 |
R5FSS1_CORE0_INTR_IN_250 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_10 |
R5FSS1_CORE1_INTR_IN_250 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_11 |
R5FSS1_CORE0_INTR_IN_251 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_11 |
R5FSS1_CORE1_INTR_IN_251 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_12 |
R5FSS1_CORE0_INTR_IN_252 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_12 |
R5FSS1_CORE1_INTR_IN_252 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_13 |
R5FSS1_CORE0_INTR_IN_253 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_13 |
R5FSS1_CORE1_INTR_IN_253 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_14 |
R5FSS1_CORE0_INTR_IN_254 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_14 |
R5FSS1_CORE1_INTR_IN_254 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_15 |
R5FSS1_CORE0_INTR_IN_255 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_15 |
R5FSS1_CORE1_INTR_IN_255 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_20 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_12 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_21 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_13 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_22 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_14 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_23 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_15 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_24 |
WKUP_R5FSS0_CORE0_INTR_IN_249 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_25 |
WKUP_R5FSS0_CORE0_INTR_IN_250 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_26 |
WKUP_R5FSS0_CORE0_INTR_IN_254 |
|
C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_27 |
WKUP_R5FSS0_CORE0_INTR_IN_255 |
|
C7X256V1_CLEC_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE0_INTR_IN_113 |
|
C7X256V1_CLEC_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE1_INTR_IN_113 |
|
C7X256V1_CLEC_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE0_INTR_IN_113 |
|
C7X256V1_CLEC_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE1_INTR_IN_113 |
|
C7X256V1_CLEC_DFT_PBIST_CPU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_113 |
|
C7X256V1_CLEC_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_245 |
|
C7X256V1_CLEC_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_245 |
|
C7X256V1_CLEC_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_245 |
|
C7X256V1_CLEC_DFT_PBIST_SAFETY_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_64 |
|
C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_192 |
|
C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_1 |
ESM0_ESM_LVL_EVENT_IN_193 |
|
C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_2 |
ESM0_ESM_LVL_EVENT_IN_194 |
|
C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_3 |
ESM0_ESM_LVL_EVENT_IN_195 |
|
C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_4 |
ESM0_ESM_LVL_EVENT_IN_196 |
|
C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_5 |
ESM0_ESM_LVL_EVENT_IN_197 |
|
C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_6 |
ESM0_ESM_LVL_EVENT_IN_198 |
|
C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_OUT_7 |
ESM0_ESM_LVL_EVENT_IN_199 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_256 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_256 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_1 |
R5FSS0_CORE0_INTR_IN_257 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_1 |
R5FSS0_CORE1_INTR_IN_257 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_2 |
R5FSS0_CORE0_INTR_IN_258 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_2 |
R5FSS0_CORE1_INTR_IN_258 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_3 |
R5FSS0_CORE0_INTR_IN_259 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_3 |
R5FSS0_CORE1_INTR_IN_259 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_4 |
R5FSS0_CORE0_INTR_IN_260 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_4 |
R5FSS0_CORE1_INTR_IN_260 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_5 |
R5FSS0_CORE0_INTR_IN_261 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_5 |
R5FSS0_CORE1_INTR_IN_261 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_6 |
R5FSS0_CORE0_INTR_IN_262 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_6 |
R5FSS0_CORE1_INTR_IN_262 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_7 |
R5FSS0_CORE0_INTR_IN_263 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_7 |
R5FSS0_CORE1_INTR_IN_263 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_8 |
R5FSS1_CORE0_INTR_IN_256 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_8 |
R5FSS1_CORE1_INTR_IN_256 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_9 |
R5FSS1_CORE0_INTR_IN_257 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_9 |
R5FSS1_CORE1_INTR_IN_257 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_10 |
R5FSS1_CORE0_INTR_IN_258 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_10 |
R5FSS1_CORE1_INTR_IN_258 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_11 |
R5FSS1_CORE0_INTR_IN_259 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_11 |
R5FSS1_CORE1_INTR_IN_259 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_12 |
R5FSS1_CORE0_INTR_IN_260 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_12 |
R5FSS1_CORE1_INTR_IN_260 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_13 |
R5FSS1_CORE0_INTR_IN_261 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_13 |
R5FSS1_CORE1_INTR_IN_261 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_14 |
R5FSS1_CORE0_INTR_IN_262 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_14 |
R5FSS1_CORE1_INTR_IN_262 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_15 |
R5FSS1_CORE0_INTR_IN_263 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_15 |
R5FSS1_CORE1_INTR_IN_263 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_20 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_12 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_21 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_13 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_22 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_14 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_23 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_15 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_24 |
WKUP_R5FSS0_CORE0_INTR_IN_120 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_25 |
WKUP_R5FSS0_CORE0_INTR_IN_121 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_26 |
WKUP_R5FSS0_CORE0_INTR_IN_122 |
|
C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_OUT_27 |
WKUP_R5FSS0_CORE0_INTR_IN_165 |