SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The OBSCLK0 output pin is controlled by MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL register in the CTRL_MMR0 module; for more information about control registers, refer to CTRL_MMR Registers. Figure 6-25 shows a block diagram of internal OBSCLK0 mux connections.
| MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL(2)[4-0] CLK_SEL | OBSCLK0 Selection (1) |
|---|---|
| 0x0 | MAIN_PLL0_HSDIV0_CLKOUT |
| 0x1 | MAIN_PLL1_HSDIV0_CLKOUT |
| 0x2 | MAIN_PLL2_HSDIV0_CLKOUT |
| 0x3 | MAIN_PLL4_HSDIV0_CLKOUT |
| 0x4 | MAIN_PLL14_HSDIV0_CLKOUT |
| 0x5 | CLK_12M_RC |
| 0x6 | HFOSC0_CLKOUT_32K |
| 0x7 | PLLCTRL_OBSCLK |
| 0x8 | HFOSC0_CLKOUT |
| 0x9 | CLK_32K_RC |
| 0xA | CPSW0_CPTS_GENF0 |
| 0xB | CPSW0_CPTS_GENF1 |
| 0xC | MCU_PLL0_HSDIV0_CLKOUT |
| 0xD | MAIN_PLL15_HSDIV0_CLKOUT |
| 0x10 | MAIN_SYSCLK0 |
| 0x11 | DEVICE_CLKOUT_32K |
The value of the software-controlled 8-bit divider is determined by register MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL[15-8] CLK_DIV; for more information about control registers, refer to CTRL_MMR Registers.