SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The synchronous MCSPI protocol allows a controller device to initiate serial data transfers to a peripheral device. A peripheral select line (SPIEN_[n]) allows selection of an individual peripheral MCSPI device. Peripheral devices that are not selected do not interfere with MCSPI bus activities.
MCSPI offers the flexibility to modify the following parameters to adapt to the device features:
MCSPI supports any MCSPI word ranging from 4 bits to 32 bits long (the MCSPI_CH(i)CONF[11-7] WL bit field).
MCSPI word length can be changed between transmissions to allow the controller device to communicate with peripheral devices that have different requirements.
The polarity of the MCSPI enable signals is programmable (the MCSPI_CH(i)CONF[6] EPOL bit). SPIEN_[n] signals can be active high or low.
Assertion of the SPIEN_[n] signals is programmable and can be done manually or automatically. The manual assertion mode is available in single controller mode only. SPIEN_[n] can be kept active between words with the MCSPI_CH(i)CONF[20] FORCE bit.
Two consecutive words for two different peripheral devices can go along with active SPIEN_[n] signals with different polarity.
In start-bit mode a start-bit is added before the MCSPI word length to indicate how the next MCSPI word must be handled. The start-bit is enabled by setting the MCSPI_CH(i)CONF[23] SBE bit to 1. The MCSPI_CH(i)CONF[24] SBPOL bit defines the polarity of the start-bit.
In controller mode, the baud rate of the MCSPI serial clock is programmable using the 50-MHz reference clock (from the device clock management module). Table 12-95 lists the SPICLK bit rates obtained for data transfer when programming the clock divider (the MCSPI_CH(i)CONF[5-2] CLKD bit field).
| Divider | Clock Rate |
|---|---|
| 1 | 50 MHz(1) |
| 2 | 25 MHz(1) |
| 4 | 12.5 MHz |
| 8 | 6.25 MHz |
| 16 | 3.125 MHz |
| 32 | 1.5625 MHz |
| 64 | 781.25 kHz |
| 128 | 390.625 kHz |
| 256 | ~195 kHz |
| 512 | ~97.7 kHz |
| 1024 | ~48.8 kHz |
| 2048 | ~24.4 kHz |
| 4096 | ~12.2 kHz |
The polarity (the MCSPI_CH(i)CONF[1] POL bit) and the phase (the MCSPI_CH(i)CONF[0] PHA bit) of the MCSPI serial clock (SPICLK) are configurable to offer four combinations. Software selects the right combination, depending on the device. See Table 12-96 and Figure 12-83.
Data transfer is not required to update polarity, but it is configuration specific.
| Polarity (POL) | Phase (PHA) | MCSPI Mode | Description |
|---|---|---|---|
| 0 | 0 | Mode 0 | SPICLK is inactive low and sampling occurs at the rising edge. |
| 0 | 1 | Mode 1 | SPICLK is inactive low and sampling occurs at the falling edge. |
| 1 | 0 | Mode 2 | SPICLK is inactive high and sampling occurs at the falling edge. |
| 1 | 1 | Mode 3 | SPICLK is inactive high and sampling occurs at the rising edge. |
Figure 12-83 Phase and
Polarity Combinations