SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths. The ATL Internal Divider divides down the ATL master clock to make ATCLK.
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| Instance Name | Physical Address |
|---|---|
| ATL0 | 0FEE 0288h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CLK_DIV_SEL | INT_DIV | |||||
| NONE | R/W | R/W | |||||
| 0h | 0h | 18h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:6 | RESERVED | NONE | 0h | Reserved |
| 5 | CLK_DIV_SEL | R/W | 0h | 0: MODCLK = AWS divided by 2^16 1: MODCLK = AWS divided by 2^12 Reset Source: mod_g_rst_n |
| 4:0 | INT_DIV | R/W | 18h | Sets ratio of ATLPCLK to ATCLK Reset Source: mod_g_rst_n |