SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Controls the HSDIV that generates a 32KHz RT clock from the HFOSC0 Crystal
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| Instance Name | Physical Address |
|---|---|
| MCU_CTRL_MMR0 | 0450 8030h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| HFOSC0_CLKOUT_32K_CTRL_RESET | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| HFOSC0_CLKOUT_32K_CTRL_CLKOUT_EN | RESERVED | HFOSC0_CLKOUT_32K_CTRL_SYNC_DIS | |||||
| R/W | NONE | R/W | |||||
| 1h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | HFOSC0_CLKOUT_32K_CTRL_HSDIV | ||||||
| NONE | R/W | ||||||
| 0h | 5Eh | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | HFOSC0_CLKOUT_32K_CTRL_RESET | R/W | 0h | Asynchronous Divider Reset. Field values (others are reserved): 1'b0 - ACTIVE 1'b1 - RESET Reset Source: sys_por_rst_n |
| 30:16 | RESERVED | NONE | 0h | Reserved |
| 15 | HFOSC0_CLKOUT_32K_CTRL_CLKOUT_EN | R/W | 1h | HFOSC0_CLKOUT_32K output active Field values (others are reserved): 1'b0 - Disabled 1'b1 - Enabled Reset Source: sys_por_rst_n |
| 14:9 | RESERVED | NONE | 0h | Reserved |
| 8 | HFOSC0_CLKOUT_32K_CTRL_SYNC_DIS | R/W | 0h | HFOSC0_CLKOUT_32K Synchronize Disable This bit must be written 0. Field values (others are reserved): 1'b0 - NORMAL Reset Source: sys_por_rst_n |
| 7 | RESERVED | NONE | 0h | Reserved |
| 6:0 | HFOSC0_CLKOUT_32K_CTRL_HSDIV | R/W | 5Eh | HFOSC0_CLKOUT_32K divider: HFOSC0_CLKKOUT_32K Frequency = HFOSC0 Frequency / [8 * (hsdiv + 1)] Ex. HFOSC0 Frequency = 25MHz. hsdiv = 94 (Default) HFOSC0_CLKOUT_32K = 25MHz / (8 * (94+1)) = 26MHz / 760 = 32.894 kHz Reset Source: sys_por_rst_n |