SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Controls which internal clock is made observable on the MCU_OBSCLK output pin
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| Instance Name | Physical Address |
|---|---|
| MCU_CTRL_MMR0 | 0450 A000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | MCU_OBSCLK_CTRL_OUT_MUX_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | MCU_OBSCLK_CTRL_CLK_DIV_LD_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | MCU_OBSCLK_CTRL_CLK_DIV_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MCU_OBSCLK_CTRL_CLK_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24 | MCU_OBSCLK_CTRL_OUT_MUX_SEL_PROXY | R/W | 0h | MCU_OBSCLK pin output mux selection. Note, HFOSC0_CLK is a direct output from the HFOSC0, distinct from HFOSC0_CLKOUT. Note, when HFOSC0_CLK is selected (1'b1) the MCU_OBSCLK_CTRL_clk_sel field must be programmed to 4'b0001. Field values (others are reserved): 1'b0 - CLK_DIV_OUT 1'b1 - HFOSC0_CLK (clk_sel must be OFF) Reset Source: mod_por_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | MCU_OBSCLK_CTRL_CLK_DIV_LD_PROXY | R/W | 0h | Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed. Field values (others are reserved): 1'b0 - READY 1'b1 - LOAD Reset Source: mod_por_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:8 | MCU_OBSCLK_CTRL_CLK_DIV_PROXY | R/W | 0h | MCU_OBSCLK pin clock selection output divider Output clock is divided by clk_div+1 Reset Source: mod_por_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | MCU_OBSCLK_CTRL_CLK_SEL_PROXY | R/W | 0h | MCU_OBSCLK pin clock selection Field values (others are reserved): 4'b0000 - CLK_12M_RC 4'b0001 - OFF 4'b0010 - MCU_PLL0_HSDIV0_CLKOUT 4'b0011 - MCU_PLL0_HSDIV4_CLKOUT 4'b0100 - MCU_PLLCTRL_OBSCLK 4'b0101 - CLK_32K_RC 4'b0110 - HFOSC0_CLKOUT 4'b0111 - HFOSC0_CLKOUT_32K 4'b1000 - MCU_SYSCLK0 4'b1001 - DEVICE_CLKOUT_32K Reset Source: mod_por_rst_n |