SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Captures Reason for Warm and Main Domain Power On Resets
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| Instance Name | Physical Address |
|---|---|
| MCU_CTRL_MMR0 | 0451 8178h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RST_SRC_SAFETY_ERROR | RST_SRC_MAIN_ESM_ERROR | RESERVED | |||||
| R/W1TC | R/W1TC | NONE | |||||
| 0h | 0h | 0h | 0h | 0h | |||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RST_SRC_DM_WDT_RST | RESERVED | RST_SRC_SW_MCU_WARMRST | |||||
| R/W1TC | NONE | R/W1TC | |||||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RST_SRC_WARM_OUT_RST | RST_SRC_COLD_OUT_RST | RESERVED | RST_SRC_DEBUG_RST | |||
| NONE | R/W1TC | R/W1TC | NONE | R/W1TC | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RST_SRC_IPOR_WAKE | RESERVED | RST_SRC_THERMAL_RST | RESERVED | RESERVED | RST_SRC_MCU_RESET_PIN | |
| NONE | R/W1TC | NONE | R/W1TC | NONE | NONE | R/W1TC | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RST_SRC_SAFETY_ERROR | R/W1TC | 0h | Reset Caused by MCU ESM Error. Write 1 to Clear. Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - DETECTED Reset Source: mod_por_rst_n |
| 30 | RST_SRC_MAIN_ESM_ERROR | R/W1TC | 0h | Reset Caused by Main ESM Error. Write 1 to Clear. Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - DETECTED Reset Source: mod_por_rst_n |
| 29:26 | RESERVED | NONE | 0h | Reserved |
| 22 | RST_SRC_DM_WDT_RST | R/W1TC | 0h | Watchdog Initiated Reset. Write 1 to Clear. Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - DETECTED Reset Source: mod_por_rst_n |
| 19:17 | RESERVED | NONE | 0h | Reserved |
| 16 | RST_SRC_SW_MCU_WARMRST | R/W1TC | 0h | Software Warm Reset. Write 1 to Clear. Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - DETECTED Reset Source: mod_por_rst_n |
| 15:14 | RESERVED | NONE | 0h | Reserved |
| 13 | RST_SRC_WARM_OUT_RST | R/W1TC | 0h | SMS Warm Reset. Write 1 to Clear. Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - DETECTED Reset Source: mod_por_rst_n |
| 12 | RST_SRC_COLD_OUT_RST | R/W1TC | 0h | When set, indicates that a DMSC Cold reset occurred and reset either main or mcu domains (or both). Write 1 to clear this bit. Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - DETECTED Reset Source: mod_por_rst_n |
| 11:9 | RESERVED | NONE | 0h | Reserved |
| 8 | RST_SRC_DEBUG_RST | R/W1TC | 0h | Debug Subsystem Initiated Reset. Write 1 to Clear. Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - DETECTED Reset Source: mod_por_rst_n |
| 7 | RESERVED | NONE | 0h | Reserved |
| 6 | RST_SRC_IPOR_WAKE | R/W1TC | 0h | Wake Event Monitor Internal Power On Reset. Write 1 to Clear Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - DETECTED Reset Source: por_boot_cfg_rst_n |
| 5 | RESERVED | NONE | 0h | Reserved |
| 4 | RST_SRC_THERMAL_RST | R/W1TC | 0h | Thermal Reset. Write 1 to Clear. Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - DETECTED Reset Source: mod_por_rst_n |
| 3 | RESERVED | NONE | 0h | Reserved |
| 1 | RESERVED | NONE | 0h | Reserved |
| 0 | RST_SRC_MCU_RESET_PIN | R/W1TC | 0h | Reset Caused by MCU Reset Pin. Write 1 to Clear. Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - DETECTED Reset Source: mod_por_rst_n |