SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The FW Region 0 Permission 1 Register defines the permissions for the target br_SCRM_64_DM_CLK1_to_SCRP_32_DM_CLK4_l0 region 0 firewall.
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| Instance Name | Physical Address |
|---|---|
| WKUP_CBASS0 | 4500 8808h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PRIV_ID | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| NONSEC_USER_DEBUG | NONSEC_USER_CACHEABLE | NONSEC_USER_READ | NONSEC_USER_WRITE | NONSEC_SUPV_DEBUG | NONSEC_SUPV_CACHEABLE | NONSEC_SUPV_READ | NONSEC_SUPV_WRITE |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SEC_USER_DEBUG | SEC_USER_CACHEABLE | SEC_USER_READ | SEC_USER_WRITE | SEC_SUPV_DEBUG | SEC_SUPV_CACHEABLE | SEC_SUPV_READ | SEC_SUPV_WRITE |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | RESERVED | NONE | 0h | Reserved |
| 23:16 | PRIV_ID | R/W | 0h | Allowed privid. Reset Source: domain_default_rst_mod_g_rst_n |
| 15 | NONSEC_USER_DEBUG | R/W | 0h | Non-secure user debug allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 14 | NONSEC_USER_CACHEABLE | R/W | 0h | Non-secure user cacheable allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 13 | NONSEC_USER_READ | R/W | 0h | Non-secure user read allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 12 | NONSEC_USER_WRITE | R/W | 0h | Non-secure user write allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 11 | NONSEC_SUPV_DEBUG | R/W | 0h | Non-secure supervisor debug allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 10 | NONSEC_SUPV_CACHEABLE | R/W | 0h | Non-secure supervisor cacheable allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 9 | NONSEC_SUPV_READ | R/W | 0h | Non-secure supervisor read allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 8 | NONSEC_SUPV_WRITE | R/W | 0h | Non-secure supervisor write allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 7 | SEC_USER_DEBUG | R/W | 0h | Secure user debug allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 6 | SEC_USER_CACHEABLE | R/W | 0h | Secure user cacheable allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 5 | SEC_USER_READ | R/W | 0h | Secure user read allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 4 | SEC_USER_WRITE | R/W | 0h | Secure user write allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 3 | SEC_SUPV_DEBUG | R/W | 0h | Secure supervisor debug allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 2 | SEC_SUPV_CACHEABLE | R/W | 0h | Secure supervisor cacheable allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 1 | SEC_SUPV_READ | R/W | 0h | Secure supervisor read allowed. Reset Source: domain_default_rst_mod_g_rst_n |
| 0 | SEC_SUPV_WRITE | R/W | 0h | Secure supervisor write allowed. Reset Source: domain_default_rst_mod_g_rst_n |