SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
MDIO Control Register
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0800 0F04h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| IDLE | ENABLE | RESERVED | HIGHEST_USER_CHANNEL | ||||
| R | R/W | NONE | R | ||||
| 1h | 0h | 0h | 1h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PREAMBLE | FAULT | FAULT_DETECT_ENABLE | INT_TEST_ENABLE | RESERVED | ||
| NONE | R/W | R/W | R/W | R/W | NONE | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CLKDIV | |||||||
| R/W | |||||||
| FFh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLKDIV | |||||||
| R/W | |||||||
| FFh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | IDLE | R | 1h | MDIO state machine IDLE. Set to 1h when the state machine is in the idle state. |
| 30 | ENABLE | R/W | 0h | Enable control. Writing a 1h to this bit enables the MDIO state machine, writing a 0h disables it. If the MDIO state machine is active at the time it is disabled, it will complete the current operation before halting and setting the idle bit. If using byte access, the enable bit has to be the last bit written in this register. |
| 29 | RESERVED | NONE | 0h | Reserved |
| 28:24 | HIGHEST_USER_CHANNEL | R | 1h | Highest user channel. This field specifies the highest useraccess channel that is available in the module and is currently set to 1h. This implies that MDIOUserAccess1 is the highest available user access channel. |
| 23:21 | RESERVED | NONE | 0h | Reserved |
| 20 | PREAMBLE | R/W | 0h | Preamble disable. Writing a 1h to this bit disables this device from sending MDIO frame preambles in clause 22 mode of operation. This bit has no effect in clause 45 mode of operation. |
| 19 | FAULT | R/W | 0h | Fault indicator. This bit is set to 1h if the MDIO pins fail to read back what the device is driving onto them. This indicates a physical layer fault and the module state machine is reset. Writing a 1h to it clears this bit. |
| 18 | FAULT_DETECT_ENABLE | R/W | 0h | Fault detect enable. This bit has to be set to 1h to enable the physical layer fault detection. |
| 17 | INT_TEST_ENABLE | R/W | 0h | Interrupt test enable. This bit can be set to 1h to enable the host to set the userint and linkint bits for test purposes. |
| 16 | RESERVED | NONE | 0h | Reserved |
| 15:0 | CLKDIV | R/W | FFh | Clock Divider. This field specifies the division ratio between CLK and the frequency of MDCLK. When clkdiv is set to 0h, MDCLK is disabled and output is driven to a high logic state. MDCLK frequency = clk frequency/(clkdiv+1). |