SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
MDIO Link Interrupt Masked Register
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0800 0F14h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LINKINTMASKED | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:2 | RESERVED | NONE | 0h | Reserved |
| 1:0 | LINKINTMASKED | R/W | 0h | MDIO link change interrupt masked value. Normal mode operation: When asserted '1', a bit indicates that there was an MDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register and the corresponding CPSW_MDIO_USER_PHY_SEL_REG_k[6] LINKINT_ENABLE bit was set. CPSW_MDIO_LINK_INT_MASKED_REG[0] LINKINTMASKED and [1] LINKINTMASKED correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1h will clear the interrupt and writing 0h has no effect. These masked interrupt bits are the MDIO_LINKINT[1:0] pin values. MDIO link change interrupt masked value. State Change Mode operation: The [0] LINKINTMASKED bit will be asserted '1' when CPSW_MDIO_LINK_INT_RAW_REG[0] LINKINTRAW is asserted '1' and when the CPSW_MDIO_LINK_INT_MASK_SET_REG[0] LINKINTMASKSET bit is set to 1h. Writing a 1h will clear [0] LINKINTMASKED (and the MDIO_LINKINT[0] output) and writing 0h has no effect. The [1] LINKINTMASKED bit is not used in State Change Mode (MDIO_LINKINT[1] is therefore also unused in State Change Mode). |