SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
MDIO User Interrupt Masked Register
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0800 0F24h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | USERINTMASKED | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:2 | RESERVED | NONE | 0h | Reserved |
| 1:0 | USERINTMASKED | R/W | 0h | Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0, respectively. When asserted '1', a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has completed and the corresponding userintmaskset bit is set to 1h. Writing a 1h will clear the interrupt and writing 0h has no effect. If the [17] INT_TEST_ENABLE bit in the CPSW_MDIO_CONTROL_REG register is set, the host may set the CPSW_MDIO_USER_INT_MASKED_REG[1-0] USERINTMASKED bits to a 1h. This mode may be used for test purposes. |