SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
MDIO User Interrupt Mask Set Register
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0800 0F28h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | USERINTMASKSET | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:2 | RESERVED | NONE | 0h | Reserved |
| 1:0 | USERINTMASKSET | R/W | 0h | MDIO user interrupt mask set for CPSW_MDIO_USER_INT_MASKED_REG[1-0] USERINTMASKED, respectively. Writing a bit to 1h will enable MDIO user command complete interrupts for that particular MDIOUserAccess register. MDIO user interrupt for a particular MDIOUserAccess register is disabled if the corresponding bit is 0h. Writing a 0h to this register has no effect. |