SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
MDIO Manual Interface Register
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0800 0F30h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MDIO_MDCLK_O | MDIO_OE | MDIO_PIN | ||||
| NONE | R/W | R/W | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:3 | RESERVED | NONE | 0h | Reserved |
| 2 | MDIO_MDCLK_O | R/W | 0h | MDIO Clock Output. This value is the MDCLK_O output value when the [31] MANUALMODE bit is set in the CPSW_MDIO_POLL_REG register. |
| 1 | MDIO_OE | R/W | 0h | MDIO Output Enable. This value is inverted and output on the MDIO_OE_N output when the [31] MANUALMODE bit is set in the CPSW_MDIO_POLL_REG register. |
| 0 | MDIO_PIN | R/W | 0h | MDIO Pin Value. This is the external MDIO data pin value when the [31] MANUALMODE bit is set in the CPSW_MDIO_POLL_REG register. That is, this value is driven on the MDIO_O (the MDIO serial data output) when MDIO_OE is asserted '1'. The read value for this bit comes from MDIO_I (the MDIO serial data input). If MDIO_OE is asserted '1' and MDIO_PIN is written with a 1h then MDIO_PIN should read a 1h if there are no external devices pulling the MDIO data line low. |