SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
MDIO Poll Enable Register
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0800 0F38h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| POLL_EN | |||||||
| R/W | |||||||
| FFFFFFFFh | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| POLL_EN | |||||||
| R/W | |||||||
| FFFFFFFFh | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| POLL_EN | |||||||
| R/W | |||||||
| FFFFFFFFh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| POLL_EN | |||||||
| R/W | |||||||
| FFFFFFFFh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | POLL_EN | R/W | FFFFFFFFh | MDIO Poll Enable. When set, the bit indicates that the associated PHY will be included in polling operations. When clear, the associated PHY will not be polled. Each bit in this field is associated with a PHY. Bit zero is associated with PHY 0 and so on. Due to a limitation in the hardware, bit 31 must always be set (regardless of the value of the preamble disable bit ([20] PREAMBLE) in the CPSW_MDIO_CONTROL_REG register. However, there does not have to be a PHY at address 31. |