SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
MDIO Clause45 Register
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0800 0F3Ch + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CLAUSE45 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CLAUSE45 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CLAUSE45 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLAUSE45 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | CLAUSE45 | R/W | 0h | MDIO clause 45 mode. When a clause45 bit is cleared 0h, the PHY associated with the clause45 bit is operating in the clause 22 mode. When set 1h, the PHY associated with the clause45 bit is operating in the clause 45 mode. Bit 0 is associated with PHY 0 and so on. |