SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
CPSW Switch Control
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0802 0004h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ECC_CRC_MODE | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | CUT_THRU_ENABLE | EST_ENABLE | IET_ENABLE | EEE_ENABLE | |||
| NONE | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| P0_RX_PASS_CRC_ERR | P0_RX_PAD | P0_TX_CRC_REMOVE | P0_TX_CRC_TYPE | P8_PASS_PRI_TAGGED | P7_PASS_PRI_TAGGED | P6_PASS_PRI_TAGGED | P5_PASS_PRI_TAGGED |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| P4_PASS_PRI_TAGGED | P3_PASS_PRI_TAGGED | P2_PASS_PRI_TAGGED | P1_PASS_PRI_TAGGED | P0_PASS_PRI_TAGGED | P0_ENABLE | VLAN_AWARE | S_CN_SWITCH |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | ECC_CRC_MODE | R/W | 0h | ECC CRC Mode. 0h ECC errors induced through the ECC
aggregator flip bits in the packet headers
(not in packet data).
1h ECC errors induced through the ECC
aggregator flip bits in the packet data
(not in the packet headers). |
| 30:20 | RESERVED | NONE | 0h | Reserved |
| 19 | CUT_THRU_ENABLE | R/W | 0h | Cut Thru Enable. 0h Cut Thru disabled 1h Cut Thru enabled |
| 18 | EST_ENABLE | R/W | 0h | Enhanced Scheduled Traffic enable (EST) 0h EST is disabled 1h EST is enabled |
| 17 | IET_ENABLE | R/W | 0h | Intersperced Express Traffic enable (IET) 0h IET is disabled 1h IET is enabled |
| 16 | EEE_ENABLE | R/W | 0h | Energy Efficient Ethernet enable 0h Energy Efficient Ethernet is disabled 1h Energy Efficient Ethernet is enabled |
| 15 | P0_RX_PASS_CRC_ERR | R/W | 0h | Port 0 Pass Received CRC errors 0h Packets received with CRC errors on Port 0
are dropped.
1h Packets received with CRC errors on Port 0
are transferred to the destination ports. |
| 14 | P0_RX_PAD | R/W | 0h | Port 0 Receive Short Packet Pad 0h Short packets are dropped.
1h Short packets are padded to 64-bytes (with
pad and added CRC) if the CRC is not passed
in. Short packets are dropped if the CRC is
passed (in the Info0 word). |
| 13 | P0_TX_CRC_REMOVE | R/W | 0h | Port 0 Transmit CRC remove. 0h Do not remove the CRC on Port 0 transmit
(egress) packets.
1h Remove the CRC on all Port 0 transmit
(egress) packets. |
| 12 | P0_TX_CRC_TYPE | R/W | 0h | |
| 11 | P8_PASS_PRI_TAGGED | R/W | 0h | Port 8 Pass Priority Tagged 0h Priority tagged packets have the zero VID
replaced with the input port
Enet_P8_PORT_VLAN[11:0] on ingress.
1h Priority tagged packets are processed
unchanged. |
| 10 | P7_PASS_PRI_TAGGED | R/W | 0h | Port 7 Pass Priority Tagged 0h Priority tagged packets have the zero VID
replaced with the input port
Enet_P7_PORT_VLAN[11:0] on ingress.
1h Priority tagged packets are processed
unchanged. |
| 9 | P6_PASS_PRI_TAGGED | R/W | 0h | Port 6 Pass Priority Tagged 0h Priority tagged packets have the zero VID
replaced with the input port
Enet_P6_PORT_VLAN[11:0] on ingress.
1h Priority tagged packets are processed
unchanged. |
| 8 | P5_PASS_PRI_TAGGED | R/W | 0h | Port 5 Pass Priority Tagged 0h Priority tagged packets have the zero VID
replaced with the input port
Enet_P5_PORT_VLAN[11:0] on ingress.
1h Priority tagged packets are processed
unchanged. |
| 7 | P4_PASS_PRI_TAGGED | R/W | 0h | Port 4 Pass Priority Tagged 0h Priority tagged packets have the zero VID
replaced with the input port
Enet_P4_PORT_VLAN[11:0] on ingress.
1h Priority tagged packets are processed
unchanged. |
| 6 | P3_PASS_PRI_TAGGED | R/W | 0h | Port 3 Pass Priority Tagged 0h Priority tagged packets have the zero VID
replaced with the input port
Enet_P3_PORT_VLAN[11:0] on ingress.
1h Priority tagged packets are processed
unchanged. |
| 5 | P2_PASS_PRI_TAGGED | R/W | 0h | Port 2 Pass Priority Tagged 0h Priority tagged packets have the zero VID
replaced with the input port
Enet_P2_PORT_VLAN[11:0] on ingress.
1h Priority tagged packets are processed
unchanged. |
| 4 | P1_PASS_PRI_TAGGED | R/W | 0h | Port 1 Pass Priority Tagged 0h Priority tagged packets have the zero VID
replaced with the input port
Enet_P1_PORT_VLAN[11:0] on ingress.
1h Priority tagged packets are processed
unchanged. |
| 3 | P0_PASS_PRI_TAGGED | R/W | 0h | Port 0 Pass Priority Tagged 0h Priority tagged packets have the zero VID
replaced with the input port
P0_PORT_VLAN[11:0] on ingress.
1h Priority tagged packets are processed
unchanged. |
| 2 | P0_ENABLE | R/W | 0h | Port 0 Enable 0h CPPI port (port 0) packet operations are
disabled
1h CPPI port (port 0) packet operations are
enabled |
| 1 | VLAN_AWARE | R/W | 0h | VLAN Aware Mode: 0h CPSW_NU is in the VLAN unaware mode. 1h CPSW_NU is in the VLAN aware mode. |
| 0 | S_CN_SWITCH | R/W | 0h | Service or Customer VLAN switch. 0h Customer switch. VLAN processing uses the
inner_vlan_ltype.
1h Servide switch. VLAN processing uses the
outer_vlan_ltype. |