SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
CPSW Thru Rate
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| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0802 0020h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SL_RX_THRU_RATE | RESERVED | ||||||
| R/W | NONE | ||||||
| 3h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | P0_RX_THRU_RATE | ||||||
| NONE | R/W | ||||||
| 0h | 1h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15:12 | SL_RX_THRU_RATE | R/W | 3h | Ethernet Port Switch FIFO receive through rate. This register value is the maximum throughput of the Ethernet ports to the crossbar SCR. The default is one 8-byte word for every 3 VBUSP_GCLK periods maximum. The minimum value is 2. This is not a field that is intended to be changed by a user. |
| 11:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | P0_RX_THRU_RATE | R/W | 1h | CPPI FIFO (port 0) receive through rate. This register value is the maximum throughput of the CPPI FIFO (port 0) into the MCU_CPSW0. The minimum value is 1. This field is not intended to be changed by the user. |