SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Enet Port N FIFO STATUS
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| CPSW0 | 0802 2050h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | EST_BUFACT | EST_ADD_ERR | EST_CNT_ERR | ||||
| NONE | R | R | R | ||||
| 0h | 0h | 0h | 0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TX_E_MAC_ALLOW | |||||||
| R | |||||||
| FFh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TX_PRI_ACTIVE | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:19 | RESERVED | NONE | 0h | Reserved |
| 18 | EST_BUFACT | R | 0h | EST RAM active buffer. Indicates the active 64-word fetch buffer when CPSW_PN_EST_CONTROL_REG_k[0] EST_ONEBUF is cleared to zero. Indicates the fetch RAM address MSB when bit [0] EST_ONEBUF is set to one. |
| 17 | EST_ADD_ERR | R | 0h | EST Address Error. Indicates that the fetch RAM was read again after the previous maximum buffer address read (the previous fetch from the maximum address is reused). |
| 16 | EST_CNT_ERR | R | 0h | EST Fetch Count Error. Indicates that insufficient clocks were programmed into the fetch count and that another fetch was commanded before the previous fetch finished. |
| 15:8 | TX_E_MAC_ALLOW | R | FFh | EST transmit MAC allow. Bus that indicates the actual priorities assigned to the express queue (and inversely the priorities assigned to the prempt queue). |
| 7:0 | TX_PRI_ACTIVE | R | 0h | EST Transmit Priority Active. Bus that indicates which priorities have packets (non-empty) at the time of the register read. |